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A non-linear Electro-thermal scalable Model for High Power RF LDMOS Transistor

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Kawsar Farhad
Kawsar Farhad

This document summarizes a paper that proposes a new model for LDMOS transistors called the MM20 model. The paper describes the MM20 model structure and its extrinsic and intrinsic components. Validation results are presented showing good agreement between the modeled and measured S-parameters, drain current over varying voltages and temperatures, and output power versus input power. The conclusions are that the new MM20 model is nonlinear, temperature sensitive, optimized from experimental data, and allows for more perfect simulation of LDMOS transistor behavior than previous models.

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MM20 vs HVEKV LDMOS Model DC Only Evaluation Author: John Wood, Fellow, IEEE, Peter H. Aaen, Member, IEEE, Daren Bridges, Member, IEEE, Michael Guyonnet, Daniel S. Chan, Member, IEEE, and Nelsy Monsauret Source: IEEE transaction on microwave theory and techniques, Vol:57, No:2 February 2009
02-0000 2 Outline Why LDMOS Transistors About Models of transistor New proposed model in above mentioned paper Validation of proposed model 1
02-0000 3 Why LDMOS Transistors Laterally diffused MOS is Field effect transistor High power transistor Performance & cost RF frequency 2
02-0000 4 What is Model A way to read elements easily Is the process of generating abstract conceptual analysis 3
02-0000 5 NLDMOS Structure with Scalable Ldrift Figure 2. HV-EKV model structure with built in Rdrift. Scalable Ldrift 0.8[um]~4.8[um] Figure 1. MM20 model structure with Rdrift VerilogA code. 4
02-0000 6 The proposed Model Fig 3: Block representation of the transistor model 5
02-0000 7 Equivalent Electrical Network Fig 4: New extrinsic network with the cold-FET intrinsic circuit for a transistor with total gate periphery of 4.8 mm 6
02-0000 8 Nonlinear Intrinsic Model 7
02-0000 9 S-parameters from Measurement vs Model Fig 5: Comparison between measured and modeled s-parameters 8
02-0000 10 Load line under mismatched condition Fig 6: Load line for a Transistor operating under mismatched conditions supper-imposed upon the drain current (under pulsed operation) 9
02-0000 11 ANNs for Function Approximation and Extrapolation Fig 7: Illustration of the various regions of the drain current. The measured characterization data is indicated by region I, while regions II and III represent the extrapolation and breakdown regions. 10
02-0000 12 Prediction of device behaviour using ANNs Fig 8: Surface plot of the drain current as predicted by the full drain current model. The thick line indicates the range of voltages over which the drain current was measured. 11
02-0000 13 Behaviour of Charge state function Fig 9: Plot of Qg versus Vds and Vgs. Outside the measured region indicated by the thick line, the charge surface predicted by the neural network is smooth and very well behaved, even at extremely high voltages, which would never experienced in practice, but may be used by the simulator during convergence. 12
02-0000 14 Modeled and Measured Drain current and input power at different temperature Fig 10: Modeled and measured drain current is plotted at 25, 75 and 125 degree celsious as a function of applied gate voltage. Fig 11: Measured and modeled output power versus input power for bias current equal to 6 and 9 mA/mm 13
02-0000 15 Validation of Model This EM Model - Is Nonlinear Is Temperature sensitive Has Optimized parameter Is in good agreement with experimental data 14
02-0000 16 Conclusion New model is proposed Model is optimized from experimental data More perfect simulation is possible 15
02-0000 17 References 16
02-0000 18 References 17
02-0000 19 References 18
02-0000 20 19

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A non-linear Electro-thermal scalable Model for High Power RF LDMOS Transistor

  • 1. MM20 vs HVEKV LDMOS Model DC Only Evaluation Author: John Wood, Fellow, IEEE, Peter H. Aaen, Member, IEEE, Daren Bridges, Member, IEEE, Michael Guyonnet, Daniel S. Chan, Member, IEEE, and Nelsy Monsauret Source: IEEE transaction on microwave theory and techniques, Vol:57, No:2 February 2009
  • 2. 02-0000 2 Outline Why LDMOS Transistors About Models of transistor New proposed model in above mentioned paper Validation of proposed model 1
  • 3. 02-0000 3 Why LDMOS Transistors Laterally diffused MOS is Field effect transistor High power transistor Performance & cost RF frequency 2
  • 4. 02-0000 4 What is Model A way to read elements easily Is the process of generating abstract conceptual analysis 3
  • 5. 02-0000 5 NLDMOS Structure with Scalable Ldrift Figure 2. HV-EKV model structure with built in Rdrift. Scalable Ldrift 0.8[um]~4.8[um] Figure 1. MM20 model structure with Rdrift VerilogA code. 4
  • 6. 02-0000 6 The proposed Model Fig 3: Block representation of the transistor model 5
  • 7. 02-0000 7 Equivalent Electrical Network Fig 4: New extrinsic network with the cold-FET intrinsic circuit for a transistor with total gate periphery of 4.8 mm 6
  • 9. 02-0000 9 S-parameters from Measurement vs Model Fig 5: Comparison between measured and modeled s-parameters 8
  • 10. 02-0000 10 Load line under mismatched condition Fig 6: Load line for a Transistor operating under mismatched conditions supper-imposed upon the drain current (under pulsed operation) 9
  • 11. 02-0000 11 ANNs for Function Approximation and Extrapolation Fig 7: Illustration of the various regions of the drain current. The measured characterization data is indicated by region I, while regions II and III represent the extrapolation and breakdown regions. 10
  • 12. 02-0000 12 Prediction of device behaviour using ANNs Fig 8: Surface plot of the drain current as predicted by the full drain current model. The thick line indicates the range of voltages over which the drain current was measured. 11
  • 13. 02-0000 13 Behaviour of Charge state function Fig 9: Plot of Qg versus Vds and Vgs. Outside the measured region indicated by the thick line, the charge surface predicted by the neural network is smooth and very well behaved, even at extremely high voltages, which would never experienced in practice, but may be used by the simulator during convergence. 12
  • 14. 02-0000 14 Modeled and Measured Drain current and input power at different temperature Fig 10: Modeled and measured drain current is plotted at 25, 75 and 125 degree celsious as a function of applied gate voltage. Fig 11: Measured and modeled output power versus input power for bias current equal to 6 and 9 mA/mm 13
  • 15. 02-0000 15 Validation of Model This EM Model - Is Nonlinear Is Temperature sensitive Has Optimized parameter Is in good agreement with experimental data 14
  • 16. 02-0000 16 Conclusion New model is proposed Model is optimized from experimental data More perfect simulation is possible 15