8051 Instruction Set
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The document discusses the instruction set of the 8051 microcontroller. It describes different types of instructions such as arithmetic, data transfer, logical, branching, and bitwise logical instructions. It provides examples of instructions like ADD, MOV, INC, ANL, CLR, and CPL. It also shows the effect of sample instructions on registers and flags before and after execution.
8051 Instruction Set
- 1. The 8051 Microcontroller: Instruction Set
- 2. BYTE INSTRUCTION: MOV A, Rn (Rn ranges) MUL AB BYTE INSTRUCTION: DNJZ Rn, rel SUBB A, direct address BYTE INSTRUCTION ANL direct, #data MOV direct, #data Length of Instructions:
- 3. ARITHMETIC INSTRUCTION. DATA TRANSFER INSTRUCTION. LOGICAL INSTRUCTION. BRANCHING INSTRUCTION. LOGICAL OPERATION ON BITS INSTRUCTION. Classification of instructions:
- 4. ARITHMETIC OPERATIONS. LENGTH- 1 OR 2. FLAGS AFFECTED. Arithmetic instruction
- 5. FUNCTION. LENGTH. FLAGS AFFECTED. ADDRESSING MODE. ADD A, Rn
- 6. Before execution ADD A, R3 A 13 B R0 R1 R2 R3 31 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
- 7. After execution ADD A, R3 A 44 B R0 R1 R2 R3 31 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 1
- 8. FUNCTION. LENGTH. FLAGS AFFECTED. ADDRESSING MODE. INC Rn
- 9. Before execution INC A A 1F B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
- 10. After execution INC A A 20 B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
- 11. SOURCE TO DESTINATION. LENGTH. FLAGS AFFECTED. MOV/MOVC/MOVX Data transfer group
- 12. FUNCTION. MOV <destination byte>, <source Byte> Flags affected. Length-1, 2 or 3 Source-Destination combo.
- 13. Before execution MOV A, R7 A 00 B R0 R1 R2 R3 R4 R5 R6 R7 14 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
- 14. After execution MOV A, R7 A 14 B R0 R1 R2 R3 R4 R5 R6 R7 14 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
- 15. FUNCTION. FLAGS AFFECTED. LENGTH. COMPULSORY OPERAND. XCH A, Rn
- 16. Before execution XCH A, R5 A 27 B R0 R1 R2 R3 R4 R5 72 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
- 17. After execution XCH A, R5 A 72 B R0 R1 R2 R3 R4 R5 27 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
- 18. PERFORMS LOGICAL OPERATIONS. LENGTH-1,2 OR 3 FLAG AFFECTED. Logical group
- 19. FUNCTION. FLAGS AFFECTED. LENGTH. ANL A, R0
- 20. Before execution ANL A, R2 A 10 B R0 R1 R2 01 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
- 21. After execution ANL A, R2 A 00 B R0 R1 R2 01 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
- 22. FUNCTION. FLAGS AFFECTED. LENGTH. CPL A
- 23. Before execution CPL A A FF B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
- 24. After execution CPL A A 00 B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
- 25. TRANSFERS PROGRAM CONTROL. LENGTH. FLAGS AFFECTED. Branching Instructions
- 26. FUNCTION. LENGTH- 2 OR 3 FLAGS AFFECTED. DJNZ <byte>, <rel-address>
- 27. FUNCTION. LENGTH. FLAGS AFFECTED. JNZ rel
- 28. FUNCTIONS. PERFORMED ON BITS. LENGTH- 1 OR 2 Logical operations on Bit
- 29. FUNCTION. LENGTH- 1 OR 2 FLAGS AFFECTED. CLR bit
- 30. Before execution CLR C A FF B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 1 0 - 1 1 0 - 0
- 31. After execution CLR C A FF B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
- 32. FUNCTION. LENGTH- 1 OR 2 FLAGS AFFECTED. CPL bit
- 33. Before execution CPL C A FF B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
- 34. After execution CPL C A FF B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 1 0 - 1 1 0 - 0