![TECHNICAL SKILLS
Tool Cadence Virtuoso Schematic and Layout Editor (DRC, LVS and RC extraction).
Programming Languages C, VHDL and Verilog
Hardware expertise - Cypress PSOC kit, Altera FPGA kit
Software used Xilinx, Modelsim and Microwind.
RELEVANT DESIGN PROJECTS
M.Tech Final Year Project
1) Design of Differential Low Noise Amplifier for ISM band Applications
Team size-1, [Oct-June2015]
Low noise amplifier (LNA) being the leading component in the receiver path plays a
vital part in reducing the noise of subsequent stages and provides enough gain to
amplify the received weak signal. Key issues in the RF design such as gain, noise and
power consumptions were well understood and taken into consideration while
designing. The design of Differential Low Noise Amplifier is successfully simulated
using Cadence design tool Spectre-RF in 180nm CMOS Technology to verify its
performance. Due to the use of Differential circuit, cascode configuration and series
resonance inductor has facilitated to achieve the Noise Figure of 2.17dB, gain of
17.07dB and power consumption 11.96mW at 2.4GHz frequency.
M.Tech Semester Projects
2) Physical Design and Implementation of High Phase margin, High gain Op-
Amp Team size 1, [July-Oct 2015]
An Opamp designed for slew rate of 20袖A per sec and successfully simulated in
cadence virtuoso 180nm CMOS technology to get gain of 74.4dB and power
consumed 100mW. Layout drawn taking into consideration of fingering concept to
avoid parasitic effects and design rules DRC, LVS and ERC are verified.
3) Design of Low Power ADC using CMOS 180nm Technology
Team size -2, [Jan-May 2014]
Successive Approximation Resistor (SAR)-ADC designed for the low power and high
speed analysis. D-flip flop designed with Transmission gates provides good speed.
Schematic and layout are compared with all design rules (DRC, ERC and LVS).
4) Design of Low Power 6T-SRAM in 180nm Technology
Team size-1, [Aug-Dec 2013]
Memory design tradeoffs explored with major components like Memory cells (6T-
SRAM), Sense amplifier and Decoder. These memory blocks are designed with
optimized logics and verified the readability and write ability.
5) Design and Implementation of Six-Floor Elevator in PSOC
Team size -3, [Aug-Dec 2013]
Abstract: Elevator is designed and implemented by using PSOC creator in POSC kit.
Using graphical User Interface (GUI) basic digital blocks are configured and tested
for the functionality of 6-floor elevator. Platform: PSOC CREATOR 2.1 and PSOC-5
kit.](https://image.slidesharecdn.com/mabusabpesit-151123155029-lva1-app6891/85/Actively-seeking-for-an-opportunity-in-VLSI-domain-2-320.jpg)
![B.E Final Year Project
6) Design of 8-bit RISC Microprocessor in VHDL and Implementation on FPGA
Team size 4, [Jan-June 2013]
Processor Designed for 8 basic arithmetic and logical instructions with pipelined
technique for minimum clock cycles and Implemented on FPGA Altera kit. This
processor can be reconfigurable to 32-bit and more instruction can be added.
LAB EXPERIENCE
Assisted Analog VLSI design lab for B.E 7th
semester from Sept to Dec 2014.
Explained them the design and analysis steps of analog basic circuits such as Amplifiers and
Converters. Guided them to simulate schematic and drawing layout with basic design rules.
ACHIEVEMENTS
I was responsible for organizing sports activities in college fest NIRVANA 2013.
Was awarded the best Outgoing Student of year 2009 from Jawahar Navodaya
Vidyalaya, koppal.
My achievements in Athletics included 50 medals from school to Regional level.
Was school captain for two years 2008-09 in Jawahar Navodaya Vidyalaya, koppal
STRENGHTS
Self-motivated and Passionate for VLSI design.
Hardworking and persistence in challenges.
Consistent in academia, Good team spirit and Enthusiastic.
Efficient Leadership qualities, Supportive team member with goal oriented insight.
PERSONAL DETAILS
Date of birth : 03 June1991
Gender : Male.
Nationality : Indian.
Language : English, Hindi, Kannada, Telugu.
Address : house # 189, 2nd
ward, Atpost-Gotagi , Tq-kustagi,
DistrictKoppal State-Karnataka, India -583278
DECLARATION
I hereby declare that the details furnished above are true and correct to the best of
my knowledge and belief.
Place: Bangalore Mabusab](https://image.slidesharecdn.com/mabusabpesit-151123155029-lva1-app6891/85/Actively-seeking-for-an-opportunity-in-VLSI-domain-3-320.jpg)
Actively seeking for an opportunity in VLSI domain
- 1. Resume Mabusab Phone: +91-9901164876 M.Tech in VLSI & ES Email: mabusab034@gmail.com OBJECTIVE A highly motivated and passionate electronics engineer looking for a challenging Full-time position in high technology company, where my knowledge will be tested and given a good platform to contribute my technical skills and innovative ideas. Analog/RF CMOS IC design Layout Designing EDUCATION ADDITIONAL COURSE Integrated Course on Analog CMOS ICs and RF Design From Oct 2014 to May 2015. The objective of the course was to design and analysis of Analog/RF CMOS integrated circuits and practical analysis of relevant projects in Cadence virtuoso 180nm technology. Analog IC design topics: Analog Design basics, MOS device physics, MOS Amplifier topologies, Current Mirrors, Band gap Reference, Frequency response. RF IC design topics: RF fundamentals, Passive RLC Networks, Matching, S-parameters, Noise in MOSFET, Motivation to LNA design, Mixer Fundamentals. CONFERENCE Presented a paper Design of Narrow band Differential Low Noise Amplifier in 0.18袖m CMOS Technology for RF Receiver at the National Conference on ICT Innovations for Sustainability, R V College of Engineering Bangalore, 16th- 17th May 2015 AREA OF INTEREST Examination Board Name of the Institution Year % M.Tech (VLSI & ES) V.T.U Belgaum P.E.S Institute of Technology, Bangalore South Campus 2015 78.5 B.E (E&CE) Autonomous V.T.U Belgaum P.D.A College of Engineering, Gulbarga 2013 8.25 (C.G.P.A) 12TH C.B.S.E Jawahar Navodaya Vidyalaya, Koppal 2009 74.33 10TH C.B.S.E Jawahar Navodaya Vidyalaya, Koppal 2007 75.50
- 2. TECHNICAL SKILLS Tool Cadence Virtuoso Schematic and Layout Editor (DRC, LVS and RC extraction). Programming Languages C, VHDL and Verilog Hardware expertise - Cypress PSOC kit, Altera FPGA kit Software used Xilinx, Modelsim and Microwind. RELEVANT DESIGN PROJECTS M.Tech Final Year Project 1) Design of Differential Low Noise Amplifier for ISM band Applications Team size-1, [Oct-June2015] Low noise amplifier (LNA) being the leading component in the receiver path plays a vital part in reducing the noise of subsequent stages and provides enough gain to amplify the received weak signal. Key issues in the RF design such as gain, noise and power consumptions were well understood and taken into consideration while designing. The design of Differential Low Noise Amplifier is successfully simulated using Cadence design tool Spectre-RF in 180nm CMOS Technology to verify its performance. Due to the use of Differential circuit, cascode configuration and series resonance inductor has facilitated to achieve the Noise Figure of 2.17dB, gain of 17.07dB and power consumption 11.96mW at 2.4GHz frequency. M.Tech Semester Projects 2) Physical Design and Implementation of High Phase margin, High gain Op- Amp Team size 1, [July-Oct 2015] An Opamp designed for slew rate of 20袖A per sec and successfully simulated in cadence virtuoso 180nm CMOS technology to get gain of 74.4dB and power consumed 100mW. Layout drawn taking into consideration of fingering concept to avoid parasitic effects and design rules DRC, LVS and ERC are verified. 3) Design of Low Power ADC using CMOS 180nm Technology Team size -2, [Jan-May 2014] Successive Approximation Resistor (SAR)-ADC designed for the low power and high speed analysis. D-flip flop designed with Transmission gates provides good speed. Schematic and layout are compared with all design rules (DRC, ERC and LVS). 4) Design of Low Power 6T-SRAM in 180nm Technology Team size-1, [Aug-Dec 2013] Memory design tradeoffs explored with major components like Memory cells (6T- SRAM), Sense amplifier and Decoder. These memory blocks are designed with optimized logics and verified the readability and write ability. 5) Design and Implementation of Six-Floor Elevator in PSOC Team size -3, [Aug-Dec 2013] Abstract: Elevator is designed and implemented by using PSOC creator in POSC kit. Using graphical User Interface (GUI) basic digital blocks are configured and tested for the functionality of 6-floor elevator. Platform: PSOC CREATOR 2.1 and PSOC-5 kit.
- 3. B.E Final Year Project 6) Design of 8-bit RISC Microprocessor in VHDL and Implementation on FPGA Team size 4, [Jan-June 2013] Processor Designed for 8 basic arithmetic and logical instructions with pipelined technique for minimum clock cycles and Implemented on FPGA Altera kit. This processor can be reconfigurable to 32-bit and more instruction can be added. LAB EXPERIENCE Assisted Analog VLSI design lab for B.E 7th semester from Sept to Dec 2014. Explained them the design and analysis steps of analog basic circuits such as Amplifiers and Converters. Guided them to simulate schematic and drawing layout with basic design rules. ACHIEVEMENTS I was responsible for organizing sports activities in college fest NIRVANA 2013. Was awarded the best Outgoing Student of year 2009 from Jawahar Navodaya Vidyalaya, koppal. My achievements in Athletics included 50 medals from school to Regional level. Was school captain for two years 2008-09 in Jawahar Navodaya Vidyalaya, koppal STRENGHTS Self-motivated and Passionate for VLSI design. Hardworking and persistence in challenges. Consistent in academia, Good team spirit and Enthusiastic. Efficient Leadership qualities, Supportive team member with goal oriented insight. PERSONAL DETAILS Date of birth : 03 June1991 Gender : Male. Nationality : Indian. Language : English, Hindi, Kannada, Telugu. Address : house # 189, 2nd ward, Atpost-Gotagi , Tq-kustagi, DistrictKoppal State-Karnataka, India -583278 DECLARATION I hereby declare that the details furnished above are true and correct to the best of my knowledge and belief. Place: Bangalore Mabusab