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AgO Product Road Map

Manoj Nagesh
Manoj Nagesh

AgO is a leading provider of innovative solutions for analog, and RF Circuit optimization. AgO is based in Silicon Valley California.

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Analog and RF Optimization Road Map accelerating analog computing [email_address] [email_address] Confidential
AnXplorer 1 Circuit Level Optimization AnXplorer 2 Marco Level Optimization AnXplorer 3 System Level Optimization System Level Optimization Final Goal System Specification Package and PCB Parasitic Topology Library Behavioral Model Road Map
Package & PCB Parasitic source of Noise Signal Integrity degraded Noise Margins are decreasing Mutual Inductance Matched impedance for signal reflection Lead 2 Chip Parasitic Lead 2 PCB Parasitic Parasitic limits switching speed Electrical Requirement of Electronic Packaging
Signal Integrity Timing Distortion and Cross Talk Power Integrity Simultaneous Switching and Power Electromagnetic Interference Harmonics interfere with Communication Solution Distributed Circuit Optimization by AgO Summary Of Package and PCB Parasitc
Optimization Without AnXplore Manual Process AnXplorer 2009.12 Specification Topology Selection Optimization Spice Centering Hard Macro DRC Extraction Layout
Optimization with AnXplore AnXplorer 2009.12 Optimization with AnXplorer 1 AnXplorer 2009.12 Specification Topology Selection Optimization Spice Centering Hard Macro DRC Extraction Layout AnXplorer 1
IP Creation and Reuse Automated Layout AnXplore 2 Specification Topology Selection Optimization Spice Centering Hard Macro DRC Extraction Layout IP Lib DB Integrated Automated CAD for Hard Macro AnXplorer 2 HM Lib
Integrated CAD Flow AnXplorer 3 System Spec LSI Package Spec Topology Lib BM A N X P L O R E R A N X L O R E R Block 1 Hard Macro Block 2 Hard Macro Block n Hard Macro AnXplorer 3 Integrated CAD Framework for System Level Optimization
Our tools supports all Standard Spice Simulation If a circuit can be simulated AgO can support Limitation: Spice Simulation Capability We can optimize any type of devices supported in Spice CMOS BiCMOS BiPolar SiGe and GaAs can be supported AgO Optimization Support
AgO Analog and RF Design Flow AnXplorer 1 Optimized Data Base Layout and Extraction What if Analysis
AgO Power Op Amp Test Case Optimization AnXplorer 1 Results in 9 Hours Parameters Spec Optimized W/L DC Gain > 80 db 94 db Bandwidth > 500MHz 915 MHz Phase Margin > 60 Deg 64 Deg Power < 25 mA 18 mA Settling Time < 10 nsec 3 nsec
Increased DC Gain by 17.5 % Increased Unity Gain Bandwidth by 83 % Increased Phase Margin by 6.7 % Reduced Settling Time by 70 % Decreased Current Consumption by 28 % High Gain OpAmp Test Case Summary
Analog and RF Optimization Road Map accelerating analog computing [email_address] [email_address]

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AgO Product Road Map

  • 1. Analog and RF Optimization Road Map accelerating analog computing [email_address] [email_address] Confidential
  • 2. AnXplorer 1 Circuit Level Optimization AnXplorer 2 Marco Level Optimization AnXplorer 3 System Level Optimization System Level Optimization Final Goal System Specification Package and PCB Parasitic Topology Library Behavioral Model Road Map
  • 3. Package & PCB Parasitic source of Noise Signal Integrity degraded Noise Margins are decreasing Mutual Inductance Matched impedance for signal reflection Lead 2 Chip Parasitic Lead 2 PCB Parasitic Parasitic limits switching speed Electrical Requirement of Electronic Packaging
  • 4. Signal Integrity Timing Distortion and Cross Talk Power Integrity Simultaneous Switching and Power Electromagnetic Interference Harmonics interfere with Communication Solution Distributed Circuit Optimization by AgO Summary Of Package and PCB Parasitc
  • 5. Optimization Without AnXplore Manual Process AnXplorer 2009.12 Specification Topology Selection Optimization Spice Centering Hard Macro DRC Extraction Layout
  • 6. Optimization with AnXplore AnXplorer 2009.12 Optimization with AnXplorer 1 AnXplorer 2009.12 Specification Topology Selection Optimization Spice Centering Hard Macro DRC Extraction Layout AnXplorer 1
  • 7. IP Creation and Reuse Automated Layout AnXplore 2 Specification Topology Selection Optimization Spice Centering Hard Macro DRC Extraction Layout IP Lib DB Integrated Automated CAD for Hard Macro AnXplorer 2 HM Lib
  • 8. Integrated CAD Flow AnXplorer 3 System Spec LSI Package Spec Topology Lib BM A N X P L O R E R A N X L O R E R Block 1 Hard Macro Block 2 Hard Macro Block n Hard Macro AnXplorer 3 Integrated CAD Framework for System Level Optimization
  • 9. Our tools supports all Standard Spice Simulation If a circuit can be simulated AgO can support Limitation: Spice Simulation Capability We can optimize any type of devices supported in Spice CMOS BiCMOS BiPolar SiGe and GaAs can be supported AgO Optimization Support
  • 10. AgO Analog and RF Design Flow AnXplorer 1 Optimized Data Base Layout and Extraction What if Analysis
  • 11. AgO Power Op Amp Test Case Optimization AnXplorer 1 Results in 9 Hours Parameters Spec Optimized W/L DC Gain > 80 db 94 db Bandwidth > 500MHz 915 MHz Phase Margin > 60 Deg 64 Deg Power < 25 mA 18 mA Settling Time < 10 nsec 3 nsec
  • 12. Increased DC Gain by 17.5 % Increased Unity Gain Bandwidth by 83 % Increased Phase Margin by 6.7 % Reduced Settling Time by 70 % Decreased Current Consumption by 28 % High Gain OpAmp Test Case Summary
  • 13. Analog and RF Optimization Road Map accelerating analog computing [email_address] [email_address]