Cache coherence
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The document discusses cache coherence in multiprocessor systems. It describes the cache coherence problem that can arise when multiple processors have caches and can access shared memory. It then summarizes two primary hardware solutions: directory protocols which maintain information about which caches hold which memory lines; and snoopy cache protocols where cache controllers monitor bus traffic to maintain coherence without a directory. Finally it mentions a software-based solution relying on compiler analysis and operating system support.
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Parallel Processing Presentation2daniyalqureshi712
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This document discusses parallel processing and computer architecture. It begins by using the analogy of making sandwiches to explain the difference between sequential and parallel processing. Parallel processing allows multiple tasks to be performed simultaneously using multiple processors. The document then discusses different types of parallel processor systems like SISD, SIMD, MISD, and MIMD. It also covers considerations for multiprocessor operating system design, symmetric multiprocessor systems, bus organization, cache coherence issues, and solutions to cache coherence problems like directory and snoopy protocols.Cache Memory.pptx
Cache Memory.pptxssusere16bd9
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Cache memory is a small, fast memory located close to the CPU that stores frequently accessed data from main memory to speed up processing. It is organized into multiple levels - L1 cache is inside the CPU, L2 cache is external, and main memory is L3. The cache improves performance by reducing access time - when data is in cache it is a "hit" and very fast to access, while a "miss" requires loading from main memory which is slower. Factors like cache size, mapping technique, replacement policy, and write strategy impact how efficiently it services memory requests.Ad
Cache coherence
- 1. Cache Coherence for Multiprocessors Presented by Adesh Mishra Reg. No.:1111427 Roll No.:RD1107A44
- 2. Shared-Memory Multiprocessor all processor share a common memory, each processor have own cache. Cache Coherence Problem Solutions to Cache Coherence Hardware Policies Two Primary Categories Software
- 4. Cache Coherence Problem Multiple copy of the same data can exist in the different caches simultaneously, and if processors allowed to update their own copies freely, an inconsistent view of memory can result. Write policies : write back, write through ->In the write back policy only cache is updated and the location marked so that it can be copied later into main memory. ->In the write through policy cache and main memory are updated with every write operation.
- 5. Solutions to Cache Coherence Hardware Solution : in hardware solution the cache controller specify designed to allow it to monitor all bus requests from CPUs and IOPs. ->Directory protocol : >it collect & maintain the information about copies of lines reside . >contain the information about content of various local caches. >keeping the information up-to-date. >manage the information which caches copy of which line. Drawback only for less buses not large scale system
- 6. Snoopy Cache Protocol ->distributed responsibility for maintaining cache coherence among all of the cache controller in the multiprocessor. Basic Approach: write invalid & write update. Write invalid protocol there can be multiple readers but only one writer at a time, only one cache can write to the line. Write update protocol there can be multiple writer as well as multiple readers. ->when a processor wishes to update a shared line, the word to be distributed to all others, and caches containing that line can update it.
- 7. Software cache solution in the software based protocol relying on the operating system and Compiler. Compiler-based coherence mechanisms performed an analysis on the code to determine which data items become unsafe for caching, and the mark those item accordingly. The operating system prevent any non-cacheable items from being cached. Software Approaches are attractive because to overhead of detecting potential problems is transferred run time to compile time.
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