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CRC & TRANSMIT ERRORS
Sercel 428XL System
DOCUMENT PREPARED BY: ALEX LEVY
LAND SEISMIC OPERATIONS
SEIS.ENG01@GMAIL.COM
2016
ALEX LEVY | LAND SEISMIC OPERATIONS |

THE SEISMIC SERCEL
NETWORK
FDU &
GEOPHONES
LAUX &
LAUL
LCI
E428 CLIENT
SOFTWARE The samples of seismic data are
always from the Acquisition Node
to the Data Buffer Node.
The samples are analyzed and
compressed by the Data Buffer
Node and finally sent directly to
the Control Node through the
Asynchronous protocol.
The status and result are sent to
the Recorder Node for analysis
through the asynchronous protocol
too.

COMMUNICATION
PROTOCOL
On Line only @ 8 or 16 [Mbps].
Use SYNCHRONOUS
COMMUNICATION.
COMMUNICATION BETWEEN LAU AND FDU
On Line or Transverse @ 8 or 16 [Mbps].
Use ASYNCHRONOUS COMMUNICATION.
Full duplex.
Automatic routing.
CRC Error Checking.
COMMUNICATION BETWEEN LAU OR
LCI AND LAU

8 – 16 [Mbps]
TCP/IP PROTOCOL
100[Mbps]
ETHERNET
PROTOCOL

Data Link Layer
The protocol used on Line and secondary Transverse @ 8 or 16 [Mbps] is a
TCP IP protocol.TCP/IPPROTOCOLLAYERS
PHYSICALL Layer
TRANSPORT Layer
NETWORK Layer
 Point to Point communication (P2P).
 Communication between 2 adjacent LAU’s.
 Frame management.
 Frame CRC Checking.
 Interface between Hardware and Software
 Communication between 2 adjacent LAU’s.
 Encode cell.
 Packet CRC checking.
 Routing management.
 Communication between 2 Lau’s or LCI or Server.
 Packets management.
 Communication between 2 Lau’s or LCI or
Server.
 Message management by MULTIPLEXING /
DEMULTIPLEXING.ALEX LEVY | LAND SEISMIC
OPERATIONS |

DATA ENCAPSULATION
16 [Mbps] Frame

THE CONTROL NODE IN DETAILS!
 Interfacing with the links.
 Generating the Firing Order and sensing
the Time Break.
 Seismic line management and control.
 Auxiliary links control.
 Collecting system status data to be
returned to the HCI (Human Control
Interface).
Collecting the data from the links
(Done by the Server).
Noise editing
(Zeroing/Clipping/Diversity Stack).
Correlation and Stacking.
Done in the LCI Done in the 428XL Server

PIPELINE ARCHITECTURE
ACQUISITION
NODE & DATA
BUFFER NODE
RECORDER NODE CONTROL NODE

L
C
I
LPBX: Blaster Board Interface
A
R
C
H
I
T
E
C
T
U
R
E
LPWX: Power Management Board
LPXL: Line and Transverse Management
- This board manages the Synchronization of the spread.
- This clock is tuned @ 16,384[MHz] +/- 1 ppm (1 part per million).
Main components used on LPBX:
- TCXO: 16,384[MHz] Reference Clock for Line Synchronization.
- TCXO2: 17,920[MHz] Reference Clock for DPG Synchronization.
- Manages all the different power supply need by the other cards.
- Uses MosFet Transistor Technology:
The advantages of using this technology are:
 Allows to manage a very high frequency for the power supply.
 Reduction in the working temperature.
 Reduction of components size.
- The board is able to manage the communication through the LINE
and the TRANSVERSE.
Important:
 Remind that the LINE speed is 8[Mbps] or 16[Mbps] and
TRANSVERSE speed is 100[Mbps].
 The Flash Memory that the LCI has contains all the programs for
the DSP, FPGA and IBM.ALEX LEVY | LAND SEISMIC OPERATIONS |

AT THIS POINT REMEMBER….
8 – 16 [Mbps]
TCP/IP PROTOCOL
100[Mbps]
ETHERNET
PROTOCOL

DATA Exchange between LINE – LCI – 428XL Server
• For the SlipSweep + Navigation the Default Mode is Continuous
Asynchronous Mode.
• In the Asynchronous Mode (SLIPSWEEP MODE) for the FIRST T0 the LAU
SYNCHRONIZE the Acquisition and for the following T there’s no re-
synchronization.
• In case of Error found by the LAU during the Acquisition, the only solution
is to reset the LAU MEMORY is an Abort from Operator then apply LINE
OFF/ON.
• Retrieve Mode: The Continuous Asynchronous Mode will be the default
mode for the 428XL.
• Transmission Error During Retrieve - Transmit Time-out: the Operator has
the possibility to Retry, Cancel, or Record the Retrieve.

D
A
T
A
Sample Skew Processing
P
R
O
C
E
S
S
I
N
G
• When a control word is sent to the field units, a delay of a
few milliseconds arises between the moment the first unit
receives the word and the moment the last one receives it.
• Each repeater brings about a delay of 1.5[µs] and cables
give rise to a delay of 5[ƞs] per meter.
• That is why, the start of all FDU must be synchronized and
we need to use the following method to do it. After the line
is formed, each station unit starts to acquire data. This is fed
to the FDU, then the LAU and displayed on the HCI (Human
Computer Interface) into the screen (Seismonitor in Jline
environment), but it is not recorded. The memory of the
LAU Slave gets filled up and retains the latest samples
milliseconds of data.
• During the line forming, the microcontroller (of the LAU
master for each segment and the LCI) determines the delay
corresponding to the time associated with the selected
filter, plus the delay associated with the propagation time
for the messages between the acquisition module and each
link.
As a result, the first data processed is the data that was recorded before the order to start acquisition was received.

Sample Skew Processing
During the line forming, the microcontroller (of the LAU master for each segment and the LCI) determines
the delay corresponding to the time associated with the selected filter, plus the delay associated with the
propagation time for the messages between the acquisition module and each link.
As a result, the first data processed is the data that was recorded before the order to
start acquisition was received.
DATA PROCESSING
When a control word is sent to the field units, a delay of a few milliseconds arises between the moment
the first unit receives the word and the moment the last one receives it.
Each repeater brings about a delay of 1.5[µs] and cables give rise to a delay of 5[ƞs] per meter.
That is why, the start of all FDU must be synchronized and we need to use the following method to do it.
After the line is formed, each station unit starts to acquire data. This is fed to the FDU, then the LAU and
displayed on the HCI (Human Computer Interface) into the screen (Seismonitor in Jline environment), but
it is not recorded. The memory of the LAU Slave gets filled up and retains the latest samples milliseconds
of data.

CRC ERROR
 The transmission bits are organized in frames occurring every 1[ms].
 The frames are generated by the 428XL (LCI) central unit on its Left and
Right Transverses, and replicated by each LAUX on its Low and High Port.
 A frame is composed of 64 cells: The first cell is the frame header; the
next 63 ones are dedicated to LAU/LAU or FDU/LAU communications.
 A cell is 16 bytes long on Lines and 32 bytes long on Transverses.
FROM THE “ENCAPSULATION
OF THE DATA”

The FRAMES are used to implement TWO Communication Schemes
Each FDU writes 4 samples in a cell data field.
The addressing mode uses a token
mechanism: each FDU writes its data in
the first free cell following a frame header
and sets a busy bit (in the cell header).
The addressing mode is then sequential,
so the next FDU writes its data in the next
DATA CELL.
The communication is SYNCHRONOUS
with FDU acquisition and provides an
error detection mechanism using the CRC
field.
 FDU samples received by an LAU
are processed and compressed to
form packets that are sent back
to the 428XL central unit.
 There is no time relation with
FDU acquisition: A High Level
Protocol with error detection and
recovery is implemented.
1. FDU/LAU communication (LOW LEVEL PROTOCOL) 2. LAU/LAU communication (High Level Protocol)

TIME SYNCHRONIZATION
The FDU samples the analog input using a 256[Kbits/s] sigma-delta converter.
The sampling clock is derived from the 8.192[MHz] line frequency.
The FDU perform a first decimation process to produce 24-bit sample @ 0.25[ms] sampling rate.
Four 0.25[ms] samples are written into a cell every 1[ms].
The time difference between the generation of the 428XL frame and sampling by each FDU is
measured at line power-on with a precision of 122[ns]. This value (called T1) is measured and
stored in each LAU for each FDU it controls.
The frame header sent by the 428XL central unit contains the T0 information. The information is
received by all LAU’s and FDU’s
An LAU or FDU decodes T0 if the CRC of the frame header is correct.
The T0 information is repeated three times.

oThe TB from the shooting system is not synchronous with the
generation of the 428XL frame.
oWhen TB occurs, the 428XL measures the time from TB to the start of
the next frame with a precision of 488[ns] and writes the T0
information and the measured time (called T2) in the next frame
header.
oThe LAU uses T1+T2 time to have the data received from FDU’s
synchronized with T0.

LAUL/LAUXACQUISITION
DSP processor:
 Receives incoming frames,
 Decodes cells,
Check cell consistency and CRC,
Extract samples and stores into a 512[ms] circular buffer.
The LAU contains two processors
 IBM403 processor
 This processor stores compressed packets into an acquisition buffer.
 The acquisition buffer is sent to 428XL central unit upon request using
the LAU/LAU protocol.
 This phase (called retrieval) can be done at later date compared to
acquisition.

Transmit Error Effects
FDU to LAU Communications
 When receiving a frame from the line, the
LAU checks for cell consistency.
 When a cell CRC error is detected, the
corresponding path is displayed in orange.
 If frame headers are unaltered, the
acquisition continues.
 If frame headers are altered, then the
acquisition stops with an error such as frame
error or token error.
The TRANSMIT ERROR AFFECTS THE LINE TRANSMISSION
DIFFERENTLY DEPEENDING ON THE PROTOCOL USED
LAU to LAU Communications
The transfer of compressed sample
packets from LAU to the 428XL central unit
uses the high level protocol.
If a transmit error occurs, a packet CRC
error is detected, the wrong packet is
discarded and repeated.
Transmit error have no effect on this type
of communication.

CRC error handling algorithm
• In an event of CRC errors, rather than stopping with and error
message. An algorithm is implemented allowing the acquisition to
continue and minimizing the effect of random TRANSMIT ERROR.
• Basically this algorithm replace the FRAME where a CRC errors
occurs, the four 0.25[ms] sample of each FDU are replaced byt the
four corresponding sample of the previous frame.
• Resulting all this in a predictive algorithm.
• The corresponding path is displayed in orange and the trace affected
by CRC error during the acquisition are marked as “edited” in the
SEGD record.

Case Study

EFFECT OF CONSECUTIVE CRC ERRORS

CONCLUTIONS
• A CRC IS INSERTED TO ENABLE THE LAU TO DETECT ANY
TRANSMISSION TROUBLE.
• THE START TIME (T0) OF ALL THE FDU HAS TO BE SYNCHRONIZE IN
ORDER TO DETERMINE THE TRANSMISSIONS DELAY.
• THE CRC COMUNICATES THAT THERE WAS A SYNCHRONIZATION
ERROR.
• THE SYSTEM MINIMIZE THE EFFECT BY THE APPLICATION OF A
PREDICTIVE ALGORITHM.
• THE CRC ERROR DEGRADES THE TRACE (SIGNAL).

CONCLUTIONS
• THE TRANSMIT ERROR IS BECAUSE OF A SITUATION BETWEEN THE
FDU TO LAU; SO THE ACQUISITION STOPS WITH AN ERROR SUCH AS
FRAME ERROR OR TOKEN ERROR.
• THE TRANSMIT ERROR HAS NOT EFFECT BETWEEN LAU TO LAU
COMMUNICATION.
• THE PREDECTIVE ALGORITHM IS IN ORDER TO MINIMIZE THE CRC
ERROR.

WHY CRC & TRANSMIT ERROR?
• POOR BATERY CONDITIONS, SUCH AS MAINTENANCE, OR BATTERY
LIFE .
• POOR MAINTENANCE AT THE FIELD ELECTRONICS: FDU’S, LINKS,
LAUL, LAUX.
• GENERATION OF UNWANTED ELECTROMAGNETICS FIELD.

• References:
• Sercel User’s Manual 1; 2; 3; Technical Manual
• Data Communication Fundamentals; By Kharagpur
• Phase-Locked Loops with applications ECE 5675/4675 Lectures Note Spring
2011; By Mark A. Wickert.
• Advanced Digital Signal Processing and Noise Reduction; By Saeed V. Vaseghi.
• Crystals Oscillators Real-Time-Clocks Filters Precision Timing Magnetics
Engineered Solutions; Abracon Corporation.

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