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GATE SOLUTIONS
E L E C T R O N I C S A N D C O M M U N I C A T I O N
From (1987 - 2017)
Office : Phone :F-126, (Lower Basement), Katwaria Sarai, New Delhi-110016 011-26522064
Mobile : E-mail:
Web :
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iesmasterpublications.com, iesmaster.org

Second Edition : 2017
Typeset at : IES Master Publication, New Delhi-110016
IES MASTER PUBLICATION
F-126, (Lower Basement), Katwaria Sarai, New Delhi-110016
Phone : 011-26522064, Mobile : 8130909220, 9711853908
E-mail : ies_master@yahoo.co.in, info@iesmaster.org
Web : iesmasterpublication.org
All rights reserved.
Copyright © 2017, by IES MASTER Publications. No part of this booklet may be reproduced,
or distributed in any form or by any means, electronic, mechanical, photocopying, recording,
or otherwise or stored in a database or retrieval system without the prior permission of IES
MASTER, New Delhi. Violates are liable to be legally prosecuted.

PREFACE
It is an immense pleasure to present topic wise previous years solved paper of GATE Exam.
This booklet has come out after long observation and detailed interaction with the students
preparing for GATE exam and includes detailed explanation to all questions. The approach has
been to provide explanation in such a way that just by going through the solutions, students will
be able to understand the basic concepts and will apply these concepts in solving other questions
that might be asked in future exams.
GATE exam now a days has become more important because it not only opens the door for
higher education in institutes like IIT, IISC, NIT's but also many of the PSUs have started
inducting students on the basis of GATE score. In PSU’s, which are not inducting through GATE
route, the questions in their exams are asked from GATE previous year papers. Thus, availability
of authentic solutions to the students is the need of the day. Towards this end this booklet
becomes indispensable.
I am thankful to IES master team without whose support, I don't think, this book could have
been flawlessly produced.
Every care has been taken to bring an error free book. However comments for future improvement
are most welcome.
Mr. Kanchan Kumar Thakur
Director Ex-IES

1. Network Theory ..........................................................................................01–124
2. Signal and Systems ..................................................................................125–232
3. Electronic Devices ....................................................................................233–310
4. Analog Electronics .................................................................................... 311–440
5. Digital Circuits ...........................................................................................441–540
6. Microprocessor .........................................................................................541–566
7. Control Systems .......................................................................................567–692
8. Communications .......................................................................................693–822
9. Electromagnetics ......................................................................................823–952
10. Mathematics ...........................................................................................953–1012
11. General Aptitude ...................................................................................1013–1048
CONTENTS

Network Theory
1UNIT
Network solution methods : nodal and mesh analysis; Network theorem; superposition,
Thevenin and Norton’s, maximum power transfer; Wye-Delta transformation; Steady
state sinusoidal analysis using phasors; Time domain analysis of simple linear circuits;
solution of network equations using Laplace transform; Frequency domain analysis of
RLC circuits; Linear 2-port network parameters: driving point and transfer functions;
State equations for network
Syllabus
CONTENTS
1. Basics of Network Analysis ----------------------------------------------------- 01–24
2. DC Transients and Steady State Response -------------------------------- 25–66
3. Resonance ---------------------------------------------------------------------------- 67–75
4. Network Theorems ---------------------------------------------------------------- 76–95
5. Two Port Networks --------------------------------------------------------------- 96–114
6. Network Functions and Network Synthesis ---------------------------- 115–120
7. Network Graphs----------------------------------------------------------------- 121–124

Chapter 1
Basics of Network Analysis
1. A connection is made consisting of resistance
A in series with a parallel combination of
resistances B and C. Three resistors of the
value 10  , 5 , 2  are provided. Consider
all possible permutations of the given
resistors into the positions A, B, C, and
identify the configurations with maximum
possible overall resistance, and also the ones
with minimum possible overall resistance.
The ratio of maximum to minimum value
of the resistances (upto second decimal
place) is __________
[GATE-2017]
2. In the network shown in the figure, all
resistors are identical with R 300  . The
resistance Rab (in  ) of the network is
_____.
a
b
Rab
R=300
R
R
R
R
R R
R
R
R R
R
R
R
R
R
[GATE 2015]
3. In the given circuit, the values of V1 and V2
respectively are
+
–
+
–
V2 5A
2I
I
4
V14 4
(a) 5V, 25V (b) 10V, 30V
(c) 15V, 35V (d) 0V, 20V
[GATE 2015]
4. In the circuit shown, the switch SW is
thrown from position A to position B at time
t = 0. The energy  in J taken from the
3V source to charge the 0.1 F capacitor
from 0V to 3V is
+3V 120 B A
SW
0.1 F
t=0
(a) 0.3 (b) 0.45
(c) 0.9 (d) 3
[GATE 2015]
5. In the circuit shown, the average value of
the voltage Vab (in Volts) in steady state
condition is _____
1k 1F
b
Vab
a 1mH
5V
2k
5 sin(5000 ) t
+
–
+
–
[GATE 2015]

8010009955, 9711853908 ies_master@yahoo.co.in, info@iesmaster.orgMob. : E-mail:
Regd. office : Phone :F-126, (Upper Basement), Katwaria Sarai, New Delhi-110016 011-41013406
NETWORK THEORY 3
6. At very high frequencies, the peak output
voltage V0(in Volts) is _____
+
–
1.0sin( t)V
100 F
1k
1k
1k
1k
100 F
V0
100 F
+
–
[GATE 2015]
7. In the circuit shown, the voltage Vx (in Volts)
is _____
0.5VX
0.25VX
10
820A VX
+
–
[GATE 2015]
8. The magnitude of current (in mA) through
the resistor R2 in the figure shown is ____.
10mA 2mA
R2
R1 R3
R4
1k
2k 4k
3k
[GATE 2014]
9. Consider the configuration in the figure which
is a portion of a larger electrical network.
i5
i2
i4
i1 i6
i3
R R
R
For R 1  and currents 1i 2A , i4
= –1 A,
i5
=–4A, which one of the following is TRUE ?
(a) i6 = 5 A
(b) i3 = –4A
(c) Data is sufficient to conclude that the
supposed currents are impossible.
(d) Data is insufficient to identify the
currents i2, i3 and i6. [GATE 2014]
10. In the figure shown, the value of the current
I (in Amperes) is ______.
I
5V 1A 10
55
[GATE 2014]
11. The circuit shown in the figure represents a
RIi
A1Ii
(a) voltage controlled voltage source
(b) voltage controlled current source
(c) current controlled current source
(d) current controlled voltage source
[GATE 2014]
12. Consider a delta connection of resistors and
its equivalent star connection as shown
below. If all elements of the delta connection
are scaled by a factor k, k > 0, the elements
of the corresponding star equivalent will be
scaled by a factor of
Ra
Rb Rc
RA
RC RB
(a) k2 (b) k
(c) 1/k (d) k
[GATE 2013]
13. The average power delivered to an
impedance  4 j3 by a current
  5cos A100 t 100 is
(a) 44.2 W (b) 50 W
(c) 62.5 W (d) 125 W
[GATE 2012]

4 GATE SOLVED PAPER 1987-2017
14. The impedance looking into nodes 1 and 2
in the given circuit is
1k
9k
99Ib
Ib
100 
1
2
(a) 50 (b) 100
(c) 5 (d) 10.1k
[GATE 2012]
15. A fully charged mobile phone with a 12 V
battery is good for a 10 minute talk-time.
Assume that, during the talk-time, the
battery delivers a constant current of a 2 A
and its voltage drops linearly from 12 V to
10 V as shown in the figure. How much
energy does the battery deliver during this
talk-time?
v(t)
12 V
10V
10 min0
t
(a) 220 J (b) 12 kJ
(c) 13.2 kJ (d) 14.4 kJ
[GATE 2009]
16. In the interconnection of ideal sources
shown in the figure, it is known that the 60
V source is absorbing power.
+–
20 V
12A
60VI
+–
Which of the following can be the value of
the current source I?
(a) 10 A (b) 13 A
(c) 15 A (d) 18 A
[GATE 2009]
17. The equivalent inductance measured
between the terminals 1 and 2 for the circuit
shown in the figure is
1
2
M
L1 L2
(a) L1 + L2 + M (b) L1 + L2 – M
(c) L1 + L2 + 2M (d) L1 + L2 – 2M
[GATE 2004]
18. The dependent current source shown in
given figure
5
5V = 20 V1
V /5A1
(a) delivers 80 W (b) absorbs 80 W
(c) delivers 40 W (d) absorbs 40 W
[GATE 2002]
19. The Voltage e0 in the figure, is
12V
4 2
4 2
+
–
e0
+
–
(a) 2 V (b)
4
V
3
(c) 4 V (d) 8 V
[GATE 2001]
20. If each branch of a Delta circuit has
impedance 3 Z, then each branch of the
equivalent Wye circuit has impedance
(a)
Z
3
(b) 3 Z
(c) 3 3 Z (d)
Z
3
[GATE 2001]
21. In the given circuit, the voltage v(t) is
eat ebt
1 Hv(t)
+
–
1 1
A A
(a) at bt
e e (b) at bt
e e
(c) at bt
ae be (d) at bt
ae be
[GATE 2000]

1 Mark
1. (2.14)
2. (100)
3. (a)
4. (c)
5. (5)
6. (0.5)
7. (8)
8. (2.8)
9. (a)
10. (0.5)
11. (c)
12. (b)
13. (b)
14. (a)
15. (c)
16. (a)
17. (d)
18. (a)
19. (c)
20. (a)
21. (d)
22. (a)
23. (b)
24. (c)
25. (b)
26. (a)
27. (d)
28. (a)
29. (d)
30. (a & d)
2 Marks
1. (a)
2. (1)
3. (d)
4. (5)
5. (–1A)
6. (1.5)
7. (20)
8. (29.09)
9. (2.504)
10. (10)
11. (0.4083)
12. (2.618)
13. (c)
14. (d)
15. (c)
16. (a)
17. (a)
18. (c)
19. (b)
20. (a)
21. (None of these)
22. (d)
23. (d)
24. (d)
25. (d)
26. (b)
27. (b)
28. (d)
29. (a)
3 Marks
1. (c)

NETWORK THEORY 11
Sol–1:
A
CB
Resistor are 2, 5 and10
For maximum resistance B = 2, C = 5, A = 10
Rmax =
80
7
for minimum resistance,
A = 2, B = 5, C = 10
Rmin =
16
3
max
min
R
R
=
(80 / 7)
(16 / 3)
= 2.14
Sol–2: (100)
Req
R
R
R
R
R R R
R
R
R
R
R R RR
Req
R
R
R R R
R
R
R/2 R/2
R/2 R/2
p
q
s
r
(R=300 )
Req 2R R R 2R
[Here, branch ‘pqrs’ is removed as no
current flows through it, because it forms
a balanced bridge]
 Req
=      R R2R 2R
= 
R
R R R
3
= 100
Sol–3: (a)
5A
+
–
V2
4
4 4
I +
–
V12I
x
(1)
Applying nodal analysis at node (1), we
get
5 =
x x
2I
4 4
 
 5 =
2x x
2
4 4
   x 4I
 x = 5
Now,V1 = 5V  1x V
1 2V 5 4 V   = 0
[KVL in the outermost loop]
 V2 = 5 + 5 × 4 = 25 V
Sol–4: (c)
Initially capacitor is uncharged. For t > 0,
the circuit will be :
0.1 FC
i(t) R
120 
3V
Current in RC circuit while charging is
given by :
i(t) = 0 t/RC
V
e
R

where V0 = 3V
Power delivered by the source = P
= 3i(t) [ P = V.I]
Solutions

Also, Energy =  
t t
0 0
Pdt 3i t dt 
Capacitor gets fully charged at steady
state i.e t   .
 E =
0 t/RC
0
V
3. e dt
R



=
 
 
0 t/RC
0
13V
e
R 1 RC



   
=
0
03V C e e

   
= 3 3 0.1 0 1 J      
E = 0.9 J
Sol–5: (5)
• For AC input voltage  5 sin 5000t ,
voltage across capacitor (C) at steady
state is also sinusoidal, whose average
value is zero.
• For DC voltage = 5V, at steady state
capacitor behaves as open circuit and
inductor behaves as short circuit,
therefore circuit is
V =5Vab
1K 2KVab
– +
b a
5V
Average value of voltage across
capacitor is Vab = 5V.
Sol–6: (0.5)
At very high frequencies, capacitor
behaves as short-circuit.
 XC =
1
j C
When    , CX 0[short circuit]
When all capacitors are replaced by
short-circuit.
1.0sin( t)
1 K
1 K 1 K
1 K V0
1.0sin( t)
0.5 K
0.5K
V0
V
By voltage division rule
V0 =
0.5
V
0.5 0.5
V0 =
V
2
V0 =   1
1.0sin t
2

V0 =  0.5sin t
 0 peak
V = 0.5 Volts
Sol–7: (8)
5A 20 8
10
0.25VX
0.5VX
P
+
–
VX
Apply KCL at point P
x x x
x
V V 0.25V
0.5V 5
20 10

  
x
1 175
V 5
20 1000 2
 
   
 
x
1 3 1
V 5
20 40 2
 
   
 
x
2 3 20
V 5
40
  
 
 
x
5
V 5
8
 
 
 
 Vx = 8 Volts
Sol–8: (2.8)
Transforming current sources into
voltage sources, we get
+
–
2k
20V
1k
4k
8V
3k
i
i =
 
20 8
2 1 4 3 k

  
= 2.8 mA

NETWORK THEORY 13
Sol–9: (a)
R R
R
1
11
A
i5
i2
i1
i6
i3
C
B
i4
Given,
R 1  , 1i 2A , i4 = –1A, i5 = –4A
Applying KCL at node B,
4 1 2i i i  = 0
i2 = 1 4i i 2 1 1A   
Applying KCL at node A,
5 2 3i i i  = 0
3i = 2 5i i 1 4 3A    
Applying KCL at node C,
3 6 1i i i  = 0
6i =  1 3i i 2 5A3   
Sol–10: (0.5)
5V 1A
I
10
5 5a
Applying KCL at node a,
a aV 5 V
1
5 15

  = 0
  aa3 VV 5  = 15
4Va = 30
Va = 7.5V
 I =  aV 7.5
0.5A
15 15
Sol–11: (c)
A II i RIi
Current controlled current source
A VV i RIi
Voltage controlled voltage source
+
–
Vi
G Vm i RIi
Voltage controlled current source
+
–
Vi
R Im i RIi
Current controlled voltage source
+
–
Vi
Sol–12: (b)
Ra
Rb RA
RBRC
Rc
To convert delta to star
RC =
a b
a b c
R R
R R R 
if they are factor by k so
´
CR =
a b
a b c
kR kR
kR kR kR 
´
CR =
a b
a b c
kR R
R R R 
´
CR = k Rc
So they are also factored by k.
Sol–13: (b)
The average power delivered to a complex
impedancy R jX is given by
Pavg = 2
rmsI R
=
2
5
4
2
 
 
 
= 50 W

Sol–14: (a)
1 K
99ib
+
–
V100
9K
ib
I
2
1
D
Let voltage across 1, 2 is V and current
through it is I.
V =  bi 9000 1000 
V = –10000ib
Applying KCL at point D
ib + I + 99ib =
V
100
V
I
100
 =
V
100
I =
V
50
And the impedance equivalent will be
given by
V
I
= Z 50 
Sol–15: (c)
Energy dissipated = V.I.t Joules [V in
volts, I in ampere, t in seconds]
Here, the graph of V – t is given. The
area under V – t graph will give the
product of V & t. [V in Volts and t in
seconds]
 Energy dissipated = [Area under
graph] × I
=  1
12 10 10 60 2 Joules
2
    
= 11 10 60 2 Joules  
Energy Dissipated = 13.2 kJ
Sol–16: (a)
+
–
+ –
I
20 V
60 V
(I–12)
12A
For absorbing power by 60 V,
I – 12 < 0
So I < 12A
Sol–17: (d)
L1 L2
M
1
2
Since the flux in both coil is opposing, so
mutual inductance will be negative
compared to self inductance.
Net inductance = 1 2L M L M  
= 1 2L L 2M 
Sol–18: (a)
+
–
5
+
–
5
V1/5 AV =1 20V
V1/5 Ai1
1
Apply KVL in loop 1 ,
1
1 1 1
V
V 5i 5 i 0
5
 
    
 
 i1 = 0 A
So, voltage across 5 resistor
= 5 × 4 = 20 V
So power delivered by current source
= 20 × 4 = 80 Watts
Note : If current in a resistor flows from
low voltage to high voltage then it is
delivering power (applicable for both
voltage source or current source).
Sol–19: (c)
12V
4 2
e0 2
+
–
4
Req =   4 4 4 6
I =
12
2A
6


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