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[Duong tran] hdl_coder_logarithm_2
- 1. BO CO 畛 TI THI畉T K畉 M畉CH V畛I HDL T棚n 畛 ti: T狸m hi畛u HDL Coder trong MATLAB v Th畛c thi b畉ng ch動董ng tr狸nh t鱈nh logarithm 2 (log2) Gi畉ng vi棚n h動畛ng d畉n: ThS. NGUY畛N THANH SANG Sinh vi棚n th畛c hi畛n: TR畉N 畉I D働NG - 11520537 1
- 2. T畛NG QUAN Gi畛i thi畛u v畛 MATLAB HDL Coder Ph叩t sinh HDL code t畛 c叩c gi畉i thu畉t MATLAB Gi畉i thu畉t t鱈nh logarithm 2 (log2) Demo 2
- 3. GI畛I THI畛U V畛 MATLAB HDL CODER HDL Coder l m畛t c担ng c畛 trong MATLAB v Simulink MATLAB HDL Coder h動畛ng gi畉i thu畉t Simulink HDL Coder h動畛ng m担 h狸nh Ph叩t sinh HDL code c坦 th畛 t畛ng h畛p 動畛c cho FPGA v ASIC Verilog/ VHDL Xilinx/ Altera 3
- 4. GI畛I THI畛U V畛 MATLAB HDL CODER(tt) 畛c l畉p ph畉n c畛ng Ph叩t sinh HDL code t畛 畛ng M担 ph畛ng thi畉t k畉 MATLAB testbench/ HDL testbench 動畛c ph叩t sinh ra T畛i 動u v rng bu畛c thi畉t k畉: ti nguy棚n, critical-paths, S畛 d畛ng c叩c c担ng c畛 t畛ng h畛p, m担 ph畛ng c畛a h達ng th畛 3 4
- 5. GI畛I THI畛U V畛 MATLAB HDL CODER(tt) H動畛ng t畛i vi畛c t畉o m畉u th畛 nh畉m ki畛m ch畛ng thi畉t k畉 ch畛 kh担ng ph畉i h動畛ng t畛i vi畛c thi畉t k畉 tr棚n FPGA Ngu畛n tham kh畉o cho c叩c nh thi畉t k畉 ph畉n c畛ng 5
- 6. T畛NG QUAN Gi畛i thi畛u v畛 MATLAB HDL Coder Ph叩t sinh HDL code t畛 c叩c gi畉i thu畉t MATLAB Gi畉i thu畉t t鱈nh logarithm 2 (log2) Demo 6
- 7. PHT SINH HDL CODE T畛 CC GI畉I THU畉T MATLAB 7 Thu畉t gi畉i MATLAB Chuy畛n 畛i Floating-point sang Fixed-point Ph叩t sinh HDL code 畛ng m担 ph畛ng T畛ng h畛p ph畉n c畛ng Ki畛m ch畛ng tr棚n FPGA S畛 d畛ng MATLAB 畛 thi畉t k畉 thu畉t gi畉i, m担 ph畛ng, g畛 r畛i, ki畛m tra, v t畛i 動u thi畉t k畉 T畛 畛ng t畉o ra HDL code, ki畛m ch畛ng HDL code b畉ng testbench 動畛c ph叩t sinh ra Th畛c thi v ki畛m ch畛ng tr棚n FPGA
- 8. PHT SINH HDL CODE T畛 CC GI畉I THU畉T MATLAB (tt) 8 HDL Workflow Advisor Fixed-Point Conversion HDL Code Generation HDL Verification HDL Synthesis and Analysic
- 9. CHUY畛N 畛I T畛 FLOATING-POINT SANG FIXED-POINT C叩c thi畉t k畉 fixed-point c坦 動u i畛m: S畛 d畛ng 鱈t ti nguy棚n Ti棚u th畛 c担ng su畉t th畉p Hi畛u nng cao C叩c thi畉t k畉 floating-point kh担ng th畛 ph叩t sinh HDL code t畛ng h畛p 動畛c 9
- 10. CHUY畛N 畛I T畛 FLOATING-POINT SANG FIXED-POINT 畛 ch鱈nh x叩c v t畛c 畛 th畛c hi畛n ph畛 thu畛c vo chi畛u di word T畛 畛ng 畛 xu畉t chi畛u di word ho畉c th担ng qua ph但n t鱈ch t挑nh T畛 畛ng s畛 d畛ng bit t畉m Ki畛m ch畛ng fixed-point 動畛c ph叩t sinh ra so v畛i floating-point 10
- 11. PHT SINH HDL CODE Ph叩t sinh t畛 fixed-point MATLAB code H畛 tr畛 Verilog v VHDL Ph叩t sinh c叩c b叩o c叩o T湛y ch畛n t畛i 動u cho m畛c 鱈ch di畛n t鱈ch v t畛c 畛 11
- 12. KI畛M CH畛NG HDL CODE Ph叩t sinh HDL testbench t畛 MATLAB testbench T動董ng t叩c v畛i HDL Verifier nh畉m 畛ng m担 ph畛ng Y棚u c畉u MATLAB HDL Verifier 12
- 13. PHN TCH V T畛NG H畛P THI畉T K畉 Y棚u c畉u c叩c c担ng c畛 t畛ng h畛p t畛 c叩c hang th畛 3 Altera Quartus II Xilinx ISE Online testing H畛 tr畛 h畉n ch畉 m畛t s畛 ph畉n c畛ng 13
- 14. GI畉I THU畉T TNH LOGARITHM 2 Ph動董ng tr狸nh t畛ng qu叩t: y = log2(x) 0 x HDL Coder kh担ng h畛 tr畛 log, hay exp, X但y d畛ng gi畉i thu畉t t鱈nh logarithm 2 A Fast Binary Logarithm Algorithm (Clay S. Turner) 14
- 15. T畛NG QUAN Gi畛i thi畛u v畛 MATLAB HDL Coder Ph叩t sinh HDL code t畛 c叩c gi畉i thu畉t MATLAB Ph叩t sinh HDL code t畛 畛ng Chuy畛n 畛i t畛 Floating-point sang Fixed-point Gi畉i thu畉t t鱈nh logarithm 2 (log2) Demo 15
- 16. DEMO H動畛ng d畉n t畛ng b動畛c ph叩t sinh HDL code cho M畉ch c畛ng Gi畉i thu畉t t鱈nh logarithm 2 16
- 17. C畉M N M畛I NG働畛I L畉NG NGHE 17