Even up and down counter
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This module contains a 3-bit up/down counter and control logic. It uses registers to store the current count value (cnt) and direction (dir). On each clock cycle, the new value of cnt is assigned based on the current count, direction, and limit values. Similarly, the new value of dir is assigned based on the direction control signals. The counter can count up from 0 to 6 and down from 6 to 0, toggling the direction each time a limit is reached.
![module updown(clk,sync_rst,cnt);
inputclk,sync_rst;
output[2:0] cnt;
wire [2:0] b7,b6,b8,b5,b4;
wire s5,s6;
reg [2:0] cnt;
wire s4,s3,s2;
reg dir;
assignb7 = cnt - 2;
assignb8 = cnt + 2;
assignb6 = dir? b8 : b7;
assignb5 = s5 ? 2 : b6;
assigns5 = cnt == 0;
assigns6 = cnt == 6;
assignb4 = s6 ? 4 : b5;
always@(posedge clk)
begin
if (sync_rst) cnt<=0;
else cnt<=b4;
end](https://image.slidesharecdn.com/evenupanddowncounter-140707073137-phpapp01/85/Even-up-and-down-counter-1-320.jpg)
Even up and down counter
- 1. module updown(clk,sync_rst,cnt); inputclk,sync_rst; output[2:0] cnt; wire [2:0] b7,b6,b8,b5,b4; wire s5,s6; reg [2:0] cnt; wire s4,s3,s2; reg dir; assignb7 = cnt - 2; assignb8 = cnt + 2; assignb6 = dir? b8 : b7; assignb5 = s5 ? 2 : b6; assigns5 = cnt == 0; assigns6 = cnt == 6; assignb4 = s6 ? 4 : b5; always@(posedge clk) begin if (sync_rst) cnt<=0; else cnt<=b4; end
- 2. assigns4 = s5 ? 1 : 0; assigns3 = s6 ? 0 : 1; assigns2 = dir? s3 : s4; always@(posedge clk) begin if (sync_rst) dir<= 1; else dir<= s2; end endmodule