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Fault equivalence and fault location

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Pranoti Bachhav
Pranoti Bachhav

This document discusses fault testing for circuits. It covers why testing is done, different levels of testing from chip to system, and the basic principles of testing using a comparator. It also describes stuck-at faults, the concept of fault equivalence and rules, and provides an example. Finally, it discusses fault location and how a complete location test can distinguish faults but two faults may become functionally equivalent in the presence of an undetectable fault.

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FAULT EQUIVALENCE AND FAULT LOCATION PRESENTED BY: PRANOTI V BACHHAV ME 2ND year.
CONTENTS: 1. WHY TESTING? 2. VERIFICATION V/S TESTING. 3. LEVELS OF TESTING. 4. BASIC PRINCPLE OF TESTING. 5. STUCK AT FAULTS. 6. FAULT EQUIVALENCE AND RULES. 7. EQUIVALENCE EXAMPLE. 8. FAULT LOCATION.
WHY TESTING? To determine the presence of faults or absence of faults. To increase our confidence in proper working of circuits. For prevent future failure.
VERIFICATION V/S TESTING Two part process: Testing generation and application. Test application performed on every manufacturing device. Testing is a process by which we are trying to determine the presence of fault. Performed by simulation, hardware emulation or formal methods. Performed once prior to manufacturing. Verification is used to verify the correctness of a design.
LEVELS OF TESTING. Testing can be carried out at the level of: CHIP. BOARD. SYSTEM. NOTE: It costs 10 times more to test a device as we have to move to next higher level.
BASIC PRINCIPLE OF TESTING: CIRCUIT UNDER TEST COMPARATOR Input pattern Response Output response Good/ Bad
STUCK AT FAULTS: The circuit is modeled as an interconnection of Boolean gates. Some lines in the circuit are permanently stuck at logic 0 or logic 1. Each connecting line can have two types of faults Stuck-at-1 (s-a-1) Stuck-at-0 (s-a-0).
FAULT EQUIVALENCE: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.
EQUIVALENCE RULE:
EXAMPLE:
FAULT LOCATION: If in addition to fault detection, the goal of testing is fault location as well, we need to apply a test that not only detects the detectable faults but also distinguishes among them as much as possible. A complete location test distinguishes between every pair of distinguishable faults in a circuit. The presence of an undetectable fault may invalidate a complete location test. If f and g are two distinguishable faults, they may become functionally equivalent in the presence of an undetectable fault. A complete location test can diagnose a fault to within a functional equivalence class. This is the maximal diagnostic resolution that can be achieved. Two faults f and g are functionally equivalent under a test T if for every test vector . Functional equivalence implies equivalence under any test but equivalence under a given test does not imply functional equivalence.
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Fault equivalence and fault location

  • 1. FAULT EQUIVALENCE AND FAULT LOCATION PRESENTED BY: PRANOTI V BACHHAV ME 2ND year.
  • 2. CONTENTS: 1. WHY TESTING? 2. VERIFICATION V/S TESTING. 3. LEVELS OF TESTING. 4. BASIC PRINCPLE OF TESTING. 5. STUCK AT FAULTS. 6. FAULT EQUIVALENCE AND RULES. 7. EQUIVALENCE EXAMPLE. 8. FAULT LOCATION.
  • 3. WHY TESTING? To determine the presence of faults or absence of faults. To increase our confidence in proper working of circuits. For prevent future failure.
  • 4. VERIFICATION V/S TESTING Two part process: Testing generation and application. Test application performed on every manufacturing device. Testing is a process by which we are trying to determine the presence of fault. Performed by simulation, hardware emulation or formal methods. Performed once prior to manufacturing. Verification is used to verify the correctness of a design.
  • 5. LEVELS OF TESTING. Testing can be carried out at the level of: CHIP. BOARD. SYSTEM. NOTE: It costs 10 times more to test a device as we have to move to next higher level.
  • 6. BASIC PRINCIPLE OF TESTING: CIRCUIT UNDER TEST COMPARATOR Input pattern Response Output response Good/ Bad
  • 7. STUCK AT FAULTS: The circuit is modeled as an interconnection of Boolean gates. Some lines in the circuit are permanently stuck at logic 0 or logic 1. Each connecting line can have two types of faults Stuck-at-1 (s-a-1) Stuck-at-0 (s-a-0).
  • 8. FAULT EQUIVALENCE: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.
  • 11. FAULT LOCATION: If in addition to fault detection, the goal of testing is fault location as well, we need to apply a test that not only detects the detectable faults but also distinguishes among them as much as possible. A complete location test distinguishes between every pair of distinguishable faults in a circuit. The presence of an undetectable fault may invalidate a complete location test. If f and g are two distinguishable faults, they may become functionally equivalent in the presence of an undetectable fault. A complete location test can diagnose a fault to within a functional equivalence class. This is the maximal diagnostic resolution that can be achieved. Two faults f and g are functionally equivalent under a test T if for every test vector . Functional equivalence implies equivalence under any test but equivalence under a given test does not imply functional equivalence.