ºÝºÝߣ

ºÝºÝߣShare a Scribd company logo
YELLAPU GOUTAMI
Email:ye.gouthammi@gmail.com
Mobile: +91-8985938972
+91-8095652983
CAREER OBJECTIVE
EDUCATIONAL QUALIFICATIONS
LEVEL OF
EDUCATION
INSTITUTION BOARD/UNIVERSITY YEAR
OF
PASS-
-ING
AGGREGATE
(in %)
B.Tech (ECE) SriKrishnadevaraya University
College of Engg &
Technology
SriKrishnadevaraya
University,Anantapur 2014 77%
Diploma( ECE) Dr.B.R.Ambedkar GMR
Polytechnic college for
women,Karimnagar
State Board of
Technical
Education, A.P.
2010 83.19%
S.S.C
Balayesu Vidyalaya,Hindupur Board of Secondary
Education, A.P. 2007 85.83%
SKILLS
? Operating Systems : Windows7&8,Basic knowledge on Linux.
? Soft wares : Basic knowledge on cadence
? Packages : Ms-office.
? Software languages :Basic knowledge on core java
? Hardware languages:VHDL
EXPERIENCE
I am working as an IT Recruiter in Theron International Pvt.Ltd from July 2014 to Till date.
? I have 5 months of IT industry recruitment.
? To recruit, screen & shortlist the candidates according to the requirement from the client
side.
ACADEMIC PROJECTS
(1) Project title : Digital code lock
Technology : Embedded Systems
Role : Team Leader
Duration : 2 months
Description : An access control for doors forms a vital link in a security chain.The microcontroller based
digital lock for doors is an access control system that allows only authorized .Project uses the ¡°AT89C2051
To obtain a challenging and growth oriented career and ability to work under a team with good technical
skills and enthusiastic to learn new concepts readily.
Microcontroller¡±, 4*3 matrix keypad and LCD display,LED.By pressing the five digit code we can control
the door,i.e.if the code entered is correct door will be opened,otherwise it will alarm.
Responsibilities : Analyzing the requirements,Assigning tasks to each member , Assembling the components,
Writing code, Execution of code, Detecting errors, Rectifying the errors.
(2) Project title : Optimal Design to Reduce Static Power Dissipation of 1-bit Full Adder Cell Using Sleep transistor.
Environment : Linux Operating system.
Software used: Cadence Virtuoso
Role : Team member
Duration : 3 months
Description : As Technology scales into nanometer regime static power dissipation has become important
Metric. In this project, low leakage one bit full adder cells are proposed for mobile applications.
We introduced new transistor resizing and sleep transistor approach for one bit full adder cells to
reduce leakage power. Simulation results depicts that the proposed design leads to efficient one bit full adder cells in
terms of standby leakage power. We have performed simulations using 180nm technology in Cadence Tools with supply
voltage of 1.8V.
Responsibilities : Analyzing the requirements, Designing, Simulation.
EXTRA CURRICULAR ACTIVITIES
? Actively participated in national level Quiz competition in S.K.University.
? Participated in special camp organized by National Service scheme (NSS).
? Actively attended a work shop on Self Balancing Robots organized by Star Gaze Software& Technology
Solutions with IIT Roorkie & SKUCET.
? Participated in work shop on Digital Design organized by SKUCET associated with IETE Students form (ISF).
STRENGTHS
? Concentration at work place.
? Maintaining good relations at work place.
ACHIEVEMENTS
? Achieved first prize in Sudoku organized by SKU Herald.
? I secured 2nd
rank in class during academics of 3rd
year 1st
semester.
HOBBIES
? Playing caroms.
? Solving Sudoku.
PERSONAL DETAILS:
Name : Yellapu Goutami
Father¡¯s Name : Y.Narayanaswamy
Date of Birth : 14-04-1991
Marital Status : Single
Gender : Female
Nationality : Indian
Religion : Hindu
Languages Known : English and Telugu
DECLARATION:
I (Y.Goutami) here by certify that all the information provided above is true to the best of my Knowledge.
(YELLAPU GOUTAMI)

More Related Content

Gouthammi

  • 1. YELLAPU GOUTAMI Email:ye.gouthammi@gmail.com Mobile: +91-8985938972 +91-8095652983 CAREER OBJECTIVE EDUCATIONAL QUALIFICATIONS LEVEL OF EDUCATION INSTITUTION BOARD/UNIVERSITY YEAR OF PASS- -ING AGGREGATE (in %) B.Tech (ECE) SriKrishnadevaraya University College of Engg & Technology SriKrishnadevaraya University,Anantapur 2014 77% Diploma( ECE) Dr.B.R.Ambedkar GMR Polytechnic college for women,Karimnagar State Board of Technical Education, A.P. 2010 83.19% S.S.C Balayesu Vidyalaya,Hindupur Board of Secondary Education, A.P. 2007 85.83% SKILLS ? Operating Systems : Windows7&8,Basic knowledge on Linux. ? Soft wares : Basic knowledge on cadence ? Packages : Ms-office. ? Software languages :Basic knowledge on core java ? Hardware languages:VHDL EXPERIENCE I am working as an IT Recruiter in Theron International Pvt.Ltd from July 2014 to Till date. ? I have 5 months of IT industry recruitment. ? To recruit, screen & shortlist the candidates according to the requirement from the client side. ACADEMIC PROJECTS (1) Project title : Digital code lock Technology : Embedded Systems Role : Team Leader Duration : 2 months Description : An access control for doors forms a vital link in a security chain.The microcontroller based digital lock for doors is an access control system that allows only authorized .Project uses the ¡°AT89C2051 To obtain a challenging and growth oriented career and ability to work under a team with good technical skills and enthusiastic to learn new concepts readily.
  • 2. Microcontroller¡±, 4*3 matrix keypad and LCD display,LED.By pressing the five digit code we can control the door,i.e.if the code entered is correct door will be opened,otherwise it will alarm. Responsibilities : Analyzing the requirements,Assigning tasks to each member , Assembling the components, Writing code, Execution of code, Detecting errors, Rectifying the errors. (2) Project title : Optimal Design to Reduce Static Power Dissipation of 1-bit Full Adder Cell Using Sleep transistor. Environment : Linux Operating system. Software used: Cadence Virtuoso Role : Team member Duration : 3 months Description : As Technology scales into nanometer regime static power dissipation has become important Metric. In this project, low leakage one bit full adder cells are proposed for mobile applications. We introduced new transistor resizing and sleep transistor approach for one bit full adder cells to reduce leakage power. Simulation results depicts that the proposed design leads to efficient one bit full adder cells in terms of standby leakage power. We have performed simulations using 180nm technology in Cadence Tools with supply voltage of 1.8V. Responsibilities : Analyzing the requirements, Designing, Simulation. EXTRA CURRICULAR ACTIVITIES ? Actively participated in national level Quiz competition in S.K.University. ? Participated in special camp organized by National Service scheme (NSS). ? Actively attended a work shop on Self Balancing Robots organized by Star Gaze Software& Technology Solutions with IIT Roorkie & SKUCET. ? Participated in work shop on Digital Design organized by SKUCET associated with IETE Students form (ISF). STRENGTHS ? Concentration at work place. ? Maintaining good relations at work place. ACHIEVEMENTS ? Achieved first prize in Sudoku organized by SKU Herald. ? I secured 2nd rank in class during academics of 3rd year 1st semester. HOBBIES ? Playing caroms. ? Solving Sudoku. PERSONAL DETAILS: Name : Yellapu Goutami Father¡¯s Name : Y.Narayanaswamy Date of Birth : 14-04-1991 Marital Status : Single Gender : Female Nationality : Indian
  • 3. Religion : Hindu Languages Known : English and Telugu DECLARATION: I (Y.Goutami) here by certify that all the information provided above is true to the best of my Knowledge. (YELLAPU GOUTAMI)