ºÝºÝߣ

ºÝºÝߣShare a Scribd company logo

Ieee 2015 - 2016 Vlsi title

?Download as DOC, PDF?
?
P
pgembeddedsystem

This document lists 20 project titles from VLSI projects completed between 2015-2016. The projects cover a wide range of topics related to embedded systems and VLSI design including clock generators, arithmetic circuits, neural networks, communication circuits, error correction, and genetic algorithms.

1 of 2
Download to read offline
www.pgembeddedsystems.com VLSI PROJECT TITLES 2015-2016 S.NO PROJECT TITLE 1 A Spread Spectrum Clock Generator Using a Programmable Linear Frequency Modulator for Multipurpose Electronic Devices 2 Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation 3 Further Desensitized FIR Halfband Filters 4 A Modified Partial Product Generator for Redundant Binary Multipliers 5 Implementation of Arithmetic Operations with Time-free Spiking Neural P Systems 6 A Clock and Data Recovery Circuit With Programmable Multi-Level Phase Detector Characteristics and a Built-in Jitter Monitor 7 Unfaithful Glitch Propagation in Existing Binary Circuit Models 8 Early Skip Mode Decision for HEVC Encoder With Emphasis on Coding Quality 9 Two-Step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters 10 Energy Consumption of VLSI Decoders 11 Timing Error Tolerance in Small Core Designs for SoC Applications
www.pgembeddedsystems.com 12 40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer- Coupled Technique for SerDes Interface 13 Design and Analysis of Inexact Floating-Point Adders 14 In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers 15 Low-Cost High-Performance VLSI Architecture for Montgomery ModularMultiplication 16 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels 17 Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA 18 A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory 19 Signal Design for Multiple Antenna Systems With Spatial Multiplexing and Noncoherent Reception 20 Synthesis of Genetic Clock with Combinational Biologic Circuits

More Related Content

Ieee 2015 - 2016 Vlsi title

  • 1. www.pgembeddedsystems.com VLSI PROJECT TITLES 2015-2016 S.NO PROJECT TITLE 1 A Spread Spectrum Clock Generator Using a Programmable Linear Frequency Modulator for Multipurpose Electronic Devices 2 Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation 3 Further Desensitized FIR Halfband Filters 4 A Modified Partial Product Generator for Redundant Binary Multipliers 5 Implementation of Arithmetic Operations with Time-free Spiking Neural P Systems 6 A Clock and Data Recovery Circuit With Programmable Multi-Level Phase Detector Characteristics and a Built-in Jitter Monitor 7 Unfaithful Glitch Propagation in Existing Binary Circuit Models 8 Early Skip Mode Decision for HEVC Encoder With Emphasis on Coding Quality 9 Two-Step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters 10 Energy Consumption of VLSI Decoders 11 Timing Error Tolerance in Small Core Designs for SoC Applications
  • 2. www.pgembeddedsystems.com 12 40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer- Coupled Technique for SerDes Interface 13 Design and Analysis of Inexact Floating-Point Adders 14 In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers 15 Low-Cost High-Performance VLSI Architecture for Montgomery ModularMultiplication 16 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels 17 Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA 18 A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory 19 Signal Design for Multiple Antenna Systems With Spatial Multiplexing and Noncoherent Reception 20 Synthesis of Genetic Clock with Combinational Biologic Circuits