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Shalini Mahajan

This document describes a project to implement an image processing system on a Cyclone II FPGA using a co-design approach. The proposed work involves converting part of an image enhancement algorithm from software to hardware using the C2H compiler. A Nios II softcore processor will be used as the central processing unit in a system-on-a-programmable-chip configuration built with the Quartus II SOPC Builder. The image processing system aims to speed up image compression and enhancement tasks through hardware acceleration of critical functions.

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S.B. Jain Institute Of Technology Management & Research Presented by: Suraj Shukla Nimish Jain Akshay kale Pranay Nandanwar Yogesh Sarode Kamalnayan Khungar Under the guidance of : Prof Madhav Deshpande
INTRODUCTION
PROPOSED WORK To implement Image Processing system on Cyclone II FPGA. To convert part of that system into hardware using C2H compiler
CO-DESIGN Embedded system approach for combine modelling of software and hardware are called Co-Design . Boosts the system performance Reduces execution time
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SOPC BUILDER System-on-a-programmable-chip (SOPC) Reduced time Lesser hardware Available on Quartus II
SOFTCORE PROCESSOR A soft-core processor is a hardware description language (HDL) model of a specific processor (CPU) that can be customized for a given application and synthesized for an FPGA target. Platform independence Open-source Cores
NIOS II Second Generation Soft-Core 32 Bit RISC Microprocessor 8/16/32-bits memory controller for external PROM and SRAM 5 or 6 stages pipeline configuration Full 32-bit instruction set, data path, and address space 32 general-purpose registers 32 interrupt sources Dedicated instructions for computing 64-bit and 128- bit products of multiplication
Architecture of NIOS II processor
C2H COMPILER The award winning Nios II embedded processor C-to-Hardware (C2H) acceleration compiler is a tool that boosts the performance of time-critical ANSI C functions by converting them into hardware accelerators in the FPGA.
CYCLONE II Immensely successful 68,416 logic elements(LEs) 622 usable I/O pins High performance Low power consumption Less cost as compared to other FPGAs
FEATURES Push-button acceleration of ANSI/ISO C code GHz performance with mW power consumption Tight integration with software design flow Efficient latency-aware scheduling and pipelining of memory transactions
IMAGE PROCESSING Importance in the field of communication Obligation (Necessity) Transmitter end Compression Receiver end Decompression & Enhancement Image would be compressed & enhanced using DCT or DWT
MOTIVATION Co design to reduce time for execution FPGA supports complex systems on chip(SOC) The NIOS II soft-core processor has highest operating frequency
TOOLS TO BE USED Coding in GCC FPGA Flow Simulation: NIOS II IDE Implementation: Quartus II 8.1
Date Planned work Till 5th Aug 2012 Study of softcore processor (NIOS II) & Cyclone II FPGA (EP2C) & image enhancement algorithm. 6th Aug 2012 to 5th Sept 2012 Designing C code for image enhancement algorithm 6th Sept 2012 to 5th Oct 2012 System designing using Quartus 2 & simulation using NIOS II IDE 6th Oct 2012 to 5th Nov 2012 C2H compilation 6th Nov 2012 to 5th Dec 2012 Thesis writing
REFERENCES [1] Coelo Jr, C. J. N., Da Silva Jr., D. C., and Fernandes, A. O. Hardware software codesign of embedded systems, Proceedings of the 11th Brazilian Symposium on Integrated Circuit Design, January 1998, pp. 28. [2] Ernst, R.: Co design of embedded systems: status and trends, Proceedings of IEEE Design and Test, AprilJune 1998, pp.4554. [3] P. Chou, R. Ortega, G. Borriello, The Chinook hardware/software Co-design System, Proceedings ISSS, Cannes, France, 1995, pp. 22-27. [4] T. Ismail, A. Jerraya, Synthesis Steps and Design Models for Codesign, IEEE Computer,no. 2, pp. 44-52, Feb 1995. [5] Xiao-Wei Wang; Wei-Nan Chen; Ying Wang; Cheng-Lian Peng; A Co-design Flow for Reconfigurable Embedded Computing System with RTOS Support Embedded Software and Systems, 2009. ICESS '09. International Conference on Digital Object Identifier: 10.1109/ICESS.2009.84 Publication Year: 2009 , Page(s): 467 474
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  • 1. S.B. Jain Institute Of Technology Management & Research Presented by: Suraj Shukla Nimish Jain Akshay kale Pranay Nandanwar Yogesh Sarode Kamalnayan Khungar Under the guidance of : Prof Madhav Deshpande
  • 3. PROPOSED WORK To implement Image Processing system on Cyclone II FPGA. To convert part of that system into hardware using C2H compiler
  • 4. CO-DESIGN Embedded system approach for combine modelling of software and hardware are called Co-Design . Boosts the system performance Reduces execution time
  • 6. SOPC BUILDER System-on-a-programmable-chip (SOPC) Reduced time Lesser hardware Available on Quartus II
  • 7. SOFTCORE PROCESSOR A soft-core processor is a hardware description language (HDL) model of a specific processor (CPU) that can be customized for a given application and synthesized for an FPGA target. Platform independence Open-source Cores
  • 8. NIOS II Second Generation Soft-Core 32 Bit RISC Microprocessor 8/16/32-bits memory controller for external PROM and SRAM 5 or 6 stages pipeline configuration Full 32-bit instruction set, data path, and address space 32 general-purpose registers 32 interrupt sources Dedicated instructions for computing 64-bit and 128- bit products of multiplication
  • 9. Architecture of NIOS II processor
  • 10. C2H COMPILER The award winning Nios II embedded processor C-to-Hardware (C2H) acceleration compiler is a tool that boosts the performance of time-critical ANSI C functions by converting them into hardware accelerators in the FPGA.
  • 11. CYCLONE II Immensely successful 68,416 logic elements(LEs) 622 usable I/O pins High performance Low power consumption Less cost as compared to other FPGAs
  • 12. FEATURES Push-button acceleration of ANSI/ISO C code GHz performance with mW power consumption Tight integration with software design flow Efficient latency-aware scheduling and pipelining of memory transactions
  • 13. IMAGE PROCESSING Importance in the field of communication Obligation (Necessity) Transmitter end Compression Receiver end Decompression & Enhancement Image would be compressed & enhanced using DCT or DWT
  • 14. MOTIVATION Co design to reduce time for execution FPGA supports complex systems on chip(SOC) The NIOS II soft-core processor has highest operating frequency
  • 15. TOOLS TO BE USED Coding in GCC FPGA Flow Simulation: NIOS II IDE Implementation: Quartus II 8.1
  • 16. Date Planned work Till 5th Aug 2012 Study of softcore processor (NIOS II) & Cyclone II FPGA (EP2C) & image enhancement algorithm. 6th Aug 2012 to 5th Sept 2012 Designing C code for image enhancement algorithm 6th Sept 2012 to 5th Oct 2012 System designing using Quartus 2 & simulation using NIOS II IDE 6th Oct 2012 to 5th Nov 2012 C2H compilation 6th Nov 2012 to 5th Dec 2012 Thesis writing
  • 17. REFERENCES [1] Coelo Jr, C. J. N., Da Silva Jr., D. C., and Fernandes, A. O. Hardware software codesign of embedded systems, Proceedings of the 11th Brazilian Symposium on Integrated Circuit Design, January 1998, pp. 28. [2] Ernst, R.: Co design of embedded systems: status and trends, Proceedings of IEEE Design and Test, AprilJune 1998, pp.4554. [3] P. Chou, R. Ortega, G. Borriello, The Chinook hardware/software Co-design System, Proceedings ISSS, Cannes, France, 1995, pp. 22-27. [4] T. Ismail, A. Jerraya, Synthesis Steps and Design Models for Codesign, IEEE Computer,no. 2, pp. 44-52, Feb 1995. [5] Xiao-Wei Wang; Wei-Nan Chen; Ying Wang; Cheng-Lian Peng; A Co-design Flow for Reconfigurable Embedded Computing System with RTOS Support Embedded Software and Systems, 2009. ICESS '09. International Conference on Digital Object Identifier: 10.1109/ICESS.2009.84 Publication Year: 2009 , Page(s): 467 474