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Verilog ?? ????

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J
Jihyun Lee

Verilog ??? ??? module? module? ???? ??? ? ?? case study? ???? ????.

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module ?? ???? ? ?? module ??? ????? ? ??? ?? ??? ??? ???? ?? ?????? ? ? ? ??? ??? ?? ??? ???? ??? ??? ?? ??? ??? ? ? ModelSim ????? ? ??? ??? ? ? ?? ???? ?????? ?? ?? ??? ?? ? ???? ?? ?????? ???? ???? ???? ??? ??????. ? C???? #include? ???? ??, ????? ???? ??? ???. ? ?? ? ????? ? ???? ?? ??????? ????, ??? ???? ??? ???? ????. ? mymodule.v: ?? ?? ? tb_mymodule.v : ?????
module ?? ???? module tb_mymodule; reg in0, in1, in2; // used as input signal wire out0, out1; // used as output signal ... mymodule mm0(in0, in1, in2, out0, out1); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v
module tb_mymodule; reg in0, in1, in2; // used as input signal wire out0, out1; // used as output signal ... mymodule mm0(in0, in1, in2, out0, out1); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 1: ?? ??? ?? tb_mymodule.v? ??? ? ? ?? ???? mymodule??? ?? ??? ????. ?? ??? ? ?? ??? mymodule.v? ????? mymodule??? ??? ???? ??. mymodule? ?? 3?(in0, in1, in2)? ?? ??? 2?(out0, out1)? ??? ???????. tb_modul? mymodule? ?? ?? ??? ?? 3?? ??? 2?? ???? ??.
module tb_mymodule; reg in0, in1, in2; // used as input signal wire out0, out1; // used as output signal ... mymodule mm0(in0, in1, in2, out0, out1); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 1: ?? ??? ?? tb_mymodule.v? ??? ? ? ?? ???? mymodule??? ?? ??? ????. ?? ??? ? ?? ??? mymodule.v? ????? mymodule??? ??? ???? ??. mymodule? ?? 3?(in0, in1, in2)? ?? ??? 2?(out0, out1)? ??? ???????. tb_modul? mymodule? ?? ?? ??? ?? 3?? ??? 2?? ???? ??. ??? ???? ????.
module tb_mymodule; reg A, B, C; // used as input signal wire X, Y; // used as output signal ... mymodule mm0(A, B, C, X, Y); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 2: ??????? ??? ?? ?? ???? ?????? ??? ? input?? ??? ??? ??? A, B, C? ???, output?? ?? ??? ??? X, Y? ???. Case 2??? ??(?)? ???? input? input ?? ???, output? output ?? ??? ???. ? ???? ???? ??? ??? ???
module tb_mymodule; reg A, B, C; // used as input signal wire X, Y; // used as output signal ... mymodule mm0(A, B, C, X, Y); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 2: ??????? ??? ?? ?? ???? ?????? ??? ? input?? ??? ??? ??? A, B, C? ???, output?? ?? ??? ??? X, Y? ???. Case 2??? ??(?)? ???? input? input ?? ???, output? output ?? ??? ???. ? ???? ???? ??? ??? ??? ? ??? ???? ????.
module tb_mymodule; reg A, B, C; // used as input signal wire X, Y; // used as output signal ... mymodule mm0(A, B, C, X, Y); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 2: ??????? ??? ?? ?? ??????? input ??? output ??? ??? ???? ???? mymodule? ??? input ｀? ?¨? output ｀??｀ ??? ??? ??. input ??? input ???, output ??? output ??? ? ??? ?? ????.
module tb_mymodule; reg in0, in1, in2; // used as input signal wire out0, out1; // used as output signal ... mymodule mm0(out0, out1, in0, in1, in2); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 3: ?? ?? ??? Case 1?? 2? ??? ?? ????. (??? ????? ??? ????? ????? ??.) ? ???? ???? ??? ??? ???
module tb_mymodule; reg in0, in1, in2; // used as input signal wire out0, out1; // used as output signal ... mymodule mm0(out0, out1, in0, in1, in2); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 3: ?? ?? ??? Case 1? ??? ?? ????. (??? ????? ??? ????? ????? ??.) ? ???? ???? ??? ??? ??? ? ??? ???? ????.
module tb_mymodule; reg in0, in1, in2; // used as input signal wire out0, out1; // used as output signal ... mymodule mm0(out0, out1, in0, in1, in2); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 3: ?? ?? ??? ? ??? ???? ???? ??? ??? ??? ? input? output ?? ??? ??? ???? ? ????. ?? ??? ???? ?????, input/output ???? ??? ?????? ???. ?? ??? ? ??? ?? mymodule ??? ?? mm0? ??? ? ??? ?? ??? ????? ???? ??. (out0 -> in0, out1 -> in1, in0 -> in2, in1 -> out0, in2 -> out1) ??? ??? ??? ?? ??? ?? ??? ??? ??? ｀??¨? ???(??)? ?? ??? ? ? ???? ???.
module tb_mymodule; reg in0, in1, in2; // used as input signal wire out0, out1; // used as output signal ... mymodule mm0(out0, out1, in0, in1, in2); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 4: ?? ?? ?? Case 3??? ?? ??? ??? ? ? ?? ??? ??? ??? ? ? ?? ??? ??? ??? ??? ????. ???? ?? ??? ? ?? ??? ? ???? ?? ??? ?? ???? ???? ??. ? ??? ??.
module tb_mymodule; reg in0, in1, in2; // used as input signal wire out0, out1; // used as output signal ... mymodule mm0(.out0(out0), .out1(out1), .in0(in0), .in1(in1), .in2(in2)); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 4: ?? ?? ?? ? ???? ?? ? ??? ?? ??? ??? ??? ???? ????? ??. ???? ??? ???? ???? ???. .????(?????) ???? ????. ?? tb_mymodule.v?? Case 2???? input signal? reg A, B, C ?? ????? .in0(A) ?? ??? ? ??.
Summary 1. ??????? ?? ???? ??? ?? ??? ?? ?? ??? ??? ?? ??. 2. ??????? ?? ???? ??? ??? ?? input ?? ? output ??? ??? ????. 3. ? ??? ??? ??? ???, ?? ??? ???? ??? ? ?? ?? .????(?????) ???? ????. 4. ? ??? ???? ??? bit ?? ????? ?? ?? ?? ?? ??? ?? ? ??? ????. 5. ???? ? ??.

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Verilog ?? ????

  • 1. module ?? ???? ? ?? module ??? ????? ? ??? ?? ??? ??? ???? ?? ?????? ? ? ? ??? ??? ?? ??? ???? ??? ??? ?? ??? ??? ? ? ModelSim ????? ? ??? ??? ? ? ?? ???? ?????? ?? ?? ??? ?? ? ???? ?? ?????? ???? ???? ???? ??? ??????. ? C???? #include? ???? ??, ????? ???? ??? ???. ? ?? ? ????? ? ???? ?? ??????? ????, ??? ???? ??? ???? ????. ? mymodule.v: ?? ?? ? tb_mymodule.v : ?????
  • 2. module ?? ???? module tb_mymodule; reg in0, in1, in2; // used as input signal wire out0, out1; // used as output signal ... mymodule mm0(in0, in1, in2, out0, out1); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v
  • 3. module tb_mymodule; reg in0, in1, in2; // used as input signal wire out0, out1; // used as output signal ... mymodule mm0(in0, in1, in2, out0, out1); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 1: ?? ??? ?? tb_mymodule.v? ??? ? ? ?? ???? mymodule??? ?? ??? ????. ?? ??? ? ?? ??? mymodule.v? ????? mymodule??? ??? ???? ??. mymodule? ?? 3?(in0, in1, in2)? ?? ??? 2?(out0, out1)? ??? ???????. tb_modul? mymodule? ?? ?? ??? ?? 3?? ??? 2?? ???? ??.
  • 4. module tb_mymodule; reg in0, in1, in2; // used as input signal wire out0, out1; // used as output signal ... mymodule mm0(in0, in1, in2, out0, out1); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 1: ?? ??? ?? tb_mymodule.v? ??? ? ? ?? ???? mymodule??? ?? ??? ????. ?? ??? ? ?? ??? mymodule.v? ????? mymodule??? ??? ???? ??. mymodule? ?? 3?(in0, in1, in2)? ?? ??? 2?(out0, out1)? ??? ???????. tb_modul? mymodule? ?? ?? ??? ?? 3?? ??? 2?? ???? ??. ??? ???? ????.
  • 5. module tb_mymodule; reg A, B, C; // used as input signal wire X, Y; // used as output signal ... mymodule mm0(A, B, C, X, Y); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 2: ??????? ??? ?? ?? ???? ?????? ??? ? input?? ??? ??? ??? A, B, C? ???, output?? ?? ??? ??? X, Y? ???. Case 2??? ??(?)? ???? input? input ?? ???, output? output ?? ??? ???. ? ???? ???? ??? ??? ???
  • 6. module tb_mymodule; reg A, B, C; // used as input signal wire X, Y; // used as output signal ... mymodule mm0(A, B, C, X, Y); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 2: ??????? ??? ?? ?? ???? ?????? ??? ? input?? ??? ??? ??? A, B, C? ???, output?? ?? ??? ??? X, Y? ???. Case 2??? ??(?)? ???? input? input ?? ???, output? output ?? ??? ???. ? ???? ???? ??? ??? ??? ? ??? ???? ????.
  • 7. module tb_mymodule; reg A, B, C; // used as input signal wire X, Y; // used as output signal ... mymodule mm0(A, B, C, X, Y); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 2: ??????? ??? ?? ?? ??????? input ??? output ??? ??? ???? ???? mymodule? ??? input ｀? ?¨? output ｀??｀ ??? ??? ??. input ??? input ???, output ??? output ??? ? ??? ?? ????.
  • 8. module tb_mymodule; reg in0, in1, in2; // used as input signal wire out0, out1; // used as output signal ... mymodule mm0(out0, out1, in0, in1, in2); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 3: ?? ?? ??? Case 1?? 2? ??? ?? ????. (??? ????? ??? ????? ????? ??.) ? ???? ???? ??? ??? ???
  • 9. module tb_mymodule; reg in0, in1, in2; // used as input signal wire out0, out1; // used as output signal ... mymodule mm0(out0, out1, in0, in1, in2); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 3: ?? ?? ??? Case 1? ??? ?? ????. (??? ????? ??? ????? ????? ??.) ? ???? ???? ??? ??? ??? ? ??? ???? ????.
  • 10. module tb_mymodule; reg in0, in1, in2; // used as input signal wire out0, out1; // used as output signal ... mymodule mm0(out0, out1, in0, in1, in2); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 3: ?? ?? ??? ? ??? ???? ???? ??? ??? ??? ? input? output ?? ??? ??? ???? ? ????. ?? ??? ???? ?????, input/output ???? ??? ?????? ???. ?? ??? ? ??? ?? mymodule ??? ?? mm0? ??? ? ??? ?? ??? ????? ???? ??. (out0 -> in0, out1 -> in1, in0 -> in2, in1 -> out0, in2 -> out1) ??? ??? ??? ?? ??? ?? ??? ??? ??? ｀??¨? ???(??)? ?? ??? ? ? ???? ???.
  • 11. module tb_mymodule; reg in0, in1, in2; // used as input signal wire out0, out1; // used as output signal ... mymodule mm0(out0, out1, in0, in1, in2); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 4: ?? ?? ?? Case 3??? ?? ??? ??? ? ? ?? ??? ??? ??? ? ? ?? ??? ??? ??? ??? ????. ???? ?? ??? ? ?? ??? ? ???? ?? ??? ?? ???? ???? ??. ? ??? ??.
  • 12. module tb_mymodule; reg in0, in1, in2; // used as input signal wire out0, out1; // used as output signal ... mymodule mm0(.out0(out0), .out1(out1), .in0(in0), .in1(in1), .in2(in2)); ... endmodule module mymodule (in0, in1, in2, out0, out1); input in0, in1, in2; output out0, out1; ... endmodule tb_mymodule.v mymodule.v Case 4: ?? ?? ?? ? ???? ?? ? ??? ?? ??? ??? ??? ???? ????? ??. ???? ??? ???? ???? ???. .????(?????) ???? ????. ?? tb_mymodule.v?? Case 2???? input signal? reg A, B, C ?? ????? .in0(A) ?? ??? ? ??.
  • 13. Summary 1. ??????? ?? ???? ??? ?? ??? ?? ?? ??? ??? ?? ??. 2. ??????? ?? ???? ??? ??? ?? input ?? ? output ??? ??? ????. 3. ? ??? ??? ??? ???, ?? ??? ???? ??? ? ?? ?? .????(?????) ???? ????. 4. ? ??? ???? ??? bit ?? ????? ?? ?? ?? ?? ??? ?? ? ??? ????. 5. ???? ? ??.