An embedded system is a microprocessor-based system designed to perform dedicated functions. It is a combination of computer hardware and software designed to operate within a larger system. Embedded systems are found in many devices from kitchen appliances to spacecraft. They are specialized computer systems that perform specific tasks, unlike general purpose computers.
architecture of 8086 new Lecture 4new.pptxDrVikasMahor
油
The document describes the architecture and pin configuration of the 8086 microprocessor. It discusses the various pins and signals of the 8086 chip. It explains that the pins can be categorized into three groups - signals common to minimum and maximum mode, signals with special functions in minimum mode, and signals with special functions for maximum mode. The document then proceeds to describe each of the important pins and signals of the 8086 microprocessor.
POWER AMPLIFIER- introduction to power amplifier.pptxDrVikasMahor
油
A power amplifier is the last amplifier stage that delivers power to the load. Power amplifiers are classified based on the proportion of the input cycle during which the amplifying device conducts current. Class A amplifiers conduct over the entire input cycle but have low efficiency. Class B amplifiers only amplify half of the cycle, improving efficiency but introducing distortion. Class AB is a compromise with better linearity than B. Class C has very high efficiency but is used for RF where distortion is controlled by a tuned load. Class D amplifiers use pulse-width modulation for very high efficiency.
Unit IV 8086 complete ppt, architecture and instruction set.pptxDrVikasMahor
油
The document discusses the architecture of the 8086 microprocessor. It describes the two main components - the Execution Unit (EU) which executes instructions, and the Bus Interface Unit (BIU) which fetches instructions and reads/writes data from memory. The BIU uses segment registers to access different segments of memory. The EU contains registers like the accumulator, base, counter, and data registers. It also has flags in the flag register. Various addressing modes allow instructions to access memory using these registers.
8259 programmable PPI interfacing with 8085 .pptDrVikasMahor
油
This document provides information about the 8259A Programmable Interrupt Controller chip. It describes the chip's features such as supporting 8 levels of priority and being expandable up to 64 levels. It also explains how the chip works as an interrupt manager in a system, accepting requests from peripherals and determining which has highest priority to issue to the CPU. Block diagrams and explanations of the chip's registers and pins are provided.
8086 all instructions combined presentation.pptxDrVikasMahor
油
Memory segmentation allows a microprocessor with 16-bit addresses to access 1Mb of memory by dividing memory into segments for programs, data, and the stack. This facilitates separate memory areas and permits programs and data to be placed in different memory locations each time, making multitasking easier.
presentation for NEC course to defend for NEP 2020DrVikasMahor
油
This document summarizes an audit presentation on an LT-Spice tutorial for circuit simulation course given by Dr. Vikas Mahor. The objectives of the course are to teach students how to use CAD tools to analyze microelectronic circuits. The content includes installing LT-Spice software, its device models, creating and simulating circuits, and performing various circuit analyses. Upon completing the course, students will be able to analyze electrical DC circuits, build and simulate DC circuits, and write technical reports. The need for electronic circuit simulators is discussed. A list of simulation activities conducted is provided, including rectifier, clipper, clamper, logic gate, and filter circuits. Course assignments are managed via Moodle and assignment reports
introduction to Architecture of 8086 and it's applicationDrVikasMahor
油
This document describes the architecture and pin configuration of the 8086 microprocessor. It discusses the execution unit (EU) and bus interface unit (BIU) that fetch and execute instructions separately. It describes the segment registers (CS, DS, SS, ES), instruction pointer, and flags register. It provides details on the general purpose, pointer, index, and stack registers. It also covers the minimum and maximum mode pin functions and signals.
final thesis pptReductions of leakage and ground bounce noise in.pptDrVikasMahor
油
This document discusses a stacking power gating technique to reduce leakage current and ground bounce noise in high performance circuits. The stacking technique uses two sleep transistors connected in series to virtually ground a circuit block in sleep mode. This reduces leakage by raising the intermediate node voltage. Ground bounce is reduced by controlling the intermediate node voltage and turning on the second transistor in the linear region. Simulation results show the stacking technique reduces leakage by 81.71% and ground bounce by 90.39% compared to conventional power gating. However, it increases wakeup latency due to the intermediate node control.
8087 COPROCESSOR connection with 8086 and other processorsDrVikasMahor
油
The document discusses the architecture and operation of numeric coprocessors used with Intel x86 processors. It describes the 8087, 80287, and later coprocessors and their compatibility with processors like the 8086, 80286, 80386 etc. The key components of the 8087 coprocessor are described, including its 8-register stack, control and status registers, and numeric execution unit. The document also covers the circuit connections and synchronization between the x86 CPU and its numeric coprocessor to ensure proper data transfer and instruction execution.
analog to digital converter and dac finalDrVikasMahor
油
The document discusses interfacing analog to digital converters with microprocessors using an 8255 chip as an I/O port. It describes how the 8255 is used to issue start and end of conversion signals to the ADC and read the digital output. It provides examples of interfacing common ADC chips like the 0808/0809, which use successive approximation conversion. Interfacing a digital to analog converter like the AD7523 is also covered, including a program to generate a sawtooth waveform using an 8086 CPU and 8255 port.
The 8259A is an interrupt controller that manages interrupt requests from peripheral devices connected to a microprocessor. It has 8 interrupt request lines that accept signals from devices. The 8259A prioritizes the interrupt requests, masks some if needed, and issues an interrupt signal to the CPU. It then provides the CPU with the address of the interrupt service routine for the highest priority active interrupt by placing the address bytes on the data bus over 3 interrupt acknowledge pulses from the CPU. This allows efficient interrupt-driven processing of device requests.
The document provides information about the Madhav Institute of Technology & Science (MITS) in Gwalior, India. It discusses (1) the founding and history of MITS, which was established in 1957, (2) the academic programs offered including B.Tech and M.E. degrees in electronics engineering and related fields, and (3) the department of electronics engineering including its establishment, faculty, labs, projects, placements, and prominent alumni.
LTspice IV is a free SPICE circuit simulator developed by Linear Technologies. It allows users to schematically capture circuits and perform DC and transient analyses. While more advanced than simulators with schematic capture, LTspice requires knowledge of SPICE directives and has limited component libraries. However, it is widely used due to being free, fast, and powerful. The document provides guidance on using LTspice's interface and features such as adding models, performing analyses, and viewing waveforms.
Improving Surgical Robot Performance Through Seal Design.pdfBSEmarketing
油
Ever wonder how something as "simple" as a seal can impact surgical robot accuracy and reliability? Take quick a spin through this informative deck today, and use what you've learned to build a better robot tomorrow.
Mozambique, a country with vast natural resources and immense potential, nevertheless faces several economic challenges, including high unemployment, limited access to energy, and an unstable power supply. Underdeveloped infrastructure has slowed the growth of industry and hampered peoples entrepreneurial ambitions, leaving many regions in the darkliterally and figuratively.
https://www.rofinolicuco.net/blog/how-renewable-energy-can-help-mozambique-grow-its-economy
How to Build a Speed Sensor using Arduino?CircuitDigest
油
Learn how to measure speed using IR sensors in this simple DIY project. This tutorial cover circuit diagram, Sensor calibration and speed calculations and optimized Arduino code for real time speed measurements.
-Zuf辰lligurl zu
peut 辿lus silly mais les mes ishaute quils le aurais sans Les 辿tablis qui
des Louis de belle accueillis sell puss p竪re peut olds sects it's all辿tells peutall asplait suite
Il -12 ) pas cause subit lequel euros le en as d辿taill辿 de till
PILONI balo -2
ispeulit Mais anglais appareils guilt gens ils en anglais glory pile le vous pr竪s
... still que y pais vida Los play qu辿tej坦n Less via Leal su abuelos l叩stimaall) isa las
des audit elleguilt disons s'il souhait sous sirs vous lucius atoutes pouvait lets pas
il taille glacis Lieu daily qui les jeutaille pas bill Luc jean 辿cumait il taille Lacis just -Zuf辰lligurl zu
peut 辿lus silly mais les mes ishaute quils le aurais sans Les 辿tablis qui
des Louis de belle accueillis sell puss p竪re peut olds sects it's all辿tells peutall asplait suite
Il -12 ) pas cause subit lequel euros le en as d辿taill辿 de till
PILONI balo -2
ispeulit Mais anglais appareils guilt gens ils en anglais glory pile le vous pr竪s
... still que y pais vida Los play qu辿tej坦n Less via Leal su abuelos l叩stimaall) isa las
des audit elleguilt disons s'il souhait sous sirs vous lucius atoutes pouvait lets pas
il taille glacis Lieu daily qui les jeutaille pas bill Luc jean 辿cumait il taille Lacis just-Zuf辰lligurl zu
peut 辿lus silly mais les mes ishaute quils le aurais sans Les 辿tablis qui
des Louis de belle accueillis sell puss p竪re peut olds sects it's all辿tells peutall asplait suite
Il -12 ) pas cause subit lequel euros le en as d辿taill辿 de till
PILONI balo -2
ispeulit Mais anglais appareils guilt gens ils en anglais glory pile le vous pr竪s
... still que y pais vida Los play qu辿tej坦n Less via Leal su abuelos l叩stimaall) isa las
des audit elleguilt disons s'il souhait sous sirs vous lucius atoutes pouvait lets pas
il taille glacis Lieu daily qui les jeutaille pas bill Luc jean 辿cumait il taille Lacis just -Zuf辰lligurl zu
peut 辿lus silly mais les mes ishaute quils le aurais sans Les 辿tablis qui
des Louis de belle accueillis sell puss p竪re peut olds sects it's all辿tells peutall asplait suite
Il -12 ) pas cause subit lequel euros le en as d辿taill辿 de till
PILONI balo -2
ispeulit Mais anglais appareils guilt gens ils en anglais glory pile le vous pr竪s
... still que y pais vida Los play qu辿tej坦n Less via Leal su abuelos l叩stimaall) isa las
des audit elleguilt disons s'il souhait sous sirs vous lucius atoutes pouvait lets pas
il taille glacis Lieu daily qui les jeutaille pas bill Luc jean 辿cumait il taille Lacis just-Zuf辰lligurl zu
peut 辿lus silly mais les mes ishaute quils le aurais sans Les 辿tablis qui
des Louis de belle accueillis sell puss p竪re peut olds sects it's all辿tells peutall asplait suite
Il -12 ) pas cause subit lequel euros le en as d辿taill辿 de till
PILONI balo -2
ispeulit Mais anglais appareils guilt gens ils en anglais glory pile le vous pr竪s
... still que y pais vida Los play qu辿tej坦n Less via Leal su abuelos l叩stimaall) isa las
des audit elleguilt disons s'il souhait sous sirs vous lucius atoutes pouvait lets
An embedded system is a microprocessor-based system designed to perform dedicated functions. It is a combination of computer hardware and software designed to operate within a larger system. Embedded systems are found in many devices from kitchen appliances to spacecraft. They are specialized computer systems that perform specific tasks, unlike general purpose computers.
architecture of 8086 new Lecture 4new.pptxDrVikasMahor
油
The document describes the architecture and pin configuration of the 8086 microprocessor. It discusses the various pins and signals of the 8086 chip. It explains that the pins can be categorized into three groups - signals common to minimum and maximum mode, signals with special functions in minimum mode, and signals with special functions for maximum mode. The document then proceeds to describe each of the important pins and signals of the 8086 microprocessor.
POWER AMPLIFIER- introduction to power amplifier.pptxDrVikasMahor
油
A power amplifier is the last amplifier stage that delivers power to the load. Power amplifiers are classified based on the proportion of the input cycle during which the amplifying device conducts current. Class A amplifiers conduct over the entire input cycle but have low efficiency. Class B amplifiers only amplify half of the cycle, improving efficiency but introducing distortion. Class AB is a compromise with better linearity than B. Class C has very high efficiency but is used for RF where distortion is controlled by a tuned load. Class D amplifiers use pulse-width modulation for very high efficiency.
Unit IV 8086 complete ppt, architecture and instruction set.pptxDrVikasMahor
油
The document discusses the architecture of the 8086 microprocessor. It describes the two main components - the Execution Unit (EU) which executes instructions, and the Bus Interface Unit (BIU) which fetches instructions and reads/writes data from memory. The BIU uses segment registers to access different segments of memory. The EU contains registers like the accumulator, base, counter, and data registers. It also has flags in the flag register. Various addressing modes allow instructions to access memory using these registers.
8259 programmable PPI interfacing with 8085 .pptDrVikasMahor
油
This document provides information about the 8259A Programmable Interrupt Controller chip. It describes the chip's features such as supporting 8 levels of priority and being expandable up to 64 levels. It also explains how the chip works as an interrupt manager in a system, accepting requests from peripherals and determining which has highest priority to issue to the CPU. Block diagrams and explanations of the chip's registers and pins are provided.
8086 all instructions combined presentation.pptxDrVikasMahor
油
Memory segmentation allows a microprocessor with 16-bit addresses to access 1Mb of memory by dividing memory into segments for programs, data, and the stack. This facilitates separate memory areas and permits programs and data to be placed in different memory locations each time, making multitasking easier.
presentation for NEC course to defend for NEP 2020DrVikasMahor
油
This document summarizes an audit presentation on an LT-Spice tutorial for circuit simulation course given by Dr. Vikas Mahor. The objectives of the course are to teach students how to use CAD tools to analyze microelectronic circuits. The content includes installing LT-Spice software, its device models, creating and simulating circuits, and performing various circuit analyses. Upon completing the course, students will be able to analyze electrical DC circuits, build and simulate DC circuits, and write technical reports. The need for electronic circuit simulators is discussed. A list of simulation activities conducted is provided, including rectifier, clipper, clamper, logic gate, and filter circuits. Course assignments are managed via Moodle and assignment reports
introduction to Architecture of 8086 and it's applicationDrVikasMahor
油
This document describes the architecture and pin configuration of the 8086 microprocessor. It discusses the execution unit (EU) and bus interface unit (BIU) that fetch and execute instructions separately. It describes the segment registers (CS, DS, SS, ES), instruction pointer, and flags register. It provides details on the general purpose, pointer, index, and stack registers. It also covers the minimum and maximum mode pin functions and signals.
final thesis pptReductions of leakage and ground bounce noise in.pptDrVikasMahor
油
This document discusses a stacking power gating technique to reduce leakage current and ground bounce noise in high performance circuits. The stacking technique uses two sleep transistors connected in series to virtually ground a circuit block in sleep mode. This reduces leakage by raising the intermediate node voltage. Ground bounce is reduced by controlling the intermediate node voltage and turning on the second transistor in the linear region. Simulation results show the stacking technique reduces leakage by 81.71% and ground bounce by 90.39% compared to conventional power gating. However, it increases wakeup latency due to the intermediate node control.
8087 COPROCESSOR connection with 8086 and other processorsDrVikasMahor
油
The document discusses the architecture and operation of numeric coprocessors used with Intel x86 processors. It describes the 8087, 80287, and later coprocessors and their compatibility with processors like the 8086, 80286, 80386 etc. The key components of the 8087 coprocessor are described, including its 8-register stack, control and status registers, and numeric execution unit. The document also covers the circuit connections and synchronization between the x86 CPU and its numeric coprocessor to ensure proper data transfer and instruction execution.
analog to digital converter and dac finalDrVikasMahor
油
The document discusses interfacing analog to digital converters with microprocessors using an 8255 chip as an I/O port. It describes how the 8255 is used to issue start and end of conversion signals to the ADC and read the digital output. It provides examples of interfacing common ADC chips like the 0808/0809, which use successive approximation conversion. Interfacing a digital to analog converter like the AD7523 is also covered, including a program to generate a sawtooth waveform using an 8086 CPU and 8255 port.
The 8259A is an interrupt controller that manages interrupt requests from peripheral devices connected to a microprocessor. It has 8 interrupt request lines that accept signals from devices. The 8259A prioritizes the interrupt requests, masks some if needed, and issues an interrupt signal to the CPU. It then provides the CPU with the address of the interrupt service routine for the highest priority active interrupt by placing the address bytes on the data bus over 3 interrupt acknowledge pulses from the CPU. This allows efficient interrupt-driven processing of device requests.
The document provides information about the Madhav Institute of Technology & Science (MITS) in Gwalior, India. It discusses (1) the founding and history of MITS, which was established in 1957, (2) the academic programs offered including B.Tech and M.E. degrees in electronics engineering and related fields, and (3) the department of electronics engineering including its establishment, faculty, labs, projects, placements, and prominent alumni.
LTspice IV is a free SPICE circuit simulator developed by Linear Technologies. It allows users to schematically capture circuits and perform DC and transient analyses. While more advanced than simulators with schematic capture, LTspice requires knowledge of SPICE directives and has limited component libraries. However, it is widely used due to being free, fast, and powerful. The document provides guidance on using LTspice's interface and features such as adding models, performing analyses, and viewing waveforms.
Improving Surgical Robot Performance Through Seal Design.pdfBSEmarketing
油
Ever wonder how something as "simple" as a seal can impact surgical robot accuracy and reliability? Take quick a spin through this informative deck today, and use what you've learned to build a better robot tomorrow.
Mozambique, a country with vast natural resources and immense potential, nevertheless faces several economic challenges, including high unemployment, limited access to energy, and an unstable power supply. Underdeveloped infrastructure has slowed the growth of industry and hampered peoples entrepreneurial ambitions, leaving many regions in the darkliterally and figuratively.
https://www.rofinolicuco.net/blog/how-renewable-energy-can-help-mozambique-grow-its-economy
How to Build a Speed Sensor using Arduino?CircuitDigest
油
Learn how to measure speed using IR sensors in this simple DIY project. This tutorial cover circuit diagram, Sensor calibration and speed calculations and optimized Arduino code for real time speed measurements.
-Zuf辰lligurl zu
peut 辿lus silly mais les mes ishaute quils le aurais sans Les 辿tablis qui
des Louis de belle accueillis sell puss p竪re peut olds sects it's all辿tells peutall asplait suite
Il -12 ) pas cause subit lequel euros le en as d辿taill辿 de till
PILONI balo -2
ispeulit Mais anglais appareils guilt gens ils en anglais glory pile le vous pr竪s
... still que y pais vida Los play qu辿tej坦n Less via Leal su abuelos l叩stimaall) isa las
des audit elleguilt disons s'il souhait sous sirs vous lucius atoutes pouvait lets pas
il taille glacis Lieu daily qui les jeutaille pas bill Luc jean 辿cumait il taille Lacis just -Zuf辰lligurl zu
peut 辿lus silly mais les mes ishaute quils le aurais sans Les 辿tablis qui
des Louis de belle accueillis sell puss p竪re peut olds sects it's all辿tells peutall asplait suite
Il -12 ) pas cause subit lequel euros le en as d辿taill辿 de till
PILONI balo -2
ispeulit Mais anglais appareils guilt gens ils en anglais glory pile le vous pr竪s
... still que y pais vida Los play qu辿tej坦n Less via Leal su abuelos l叩stimaall) isa las
des audit elleguilt disons s'il souhait sous sirs vous lucius atoutes pouvait lets pas
il taille glacis Lieu daily qui les jeutaille pas bill Luc jean 辿cumait il taille Lacis just-Zuf辰lligurl zu
peut 辿lus silly mais les mes ishaute quils le aurais sans Les 辿tablis qui
des Louis de belle accueillis sell puss p竪re peut olds sects it's all辿tells peutall asplait suite
Il -12 ) pas cause subit lequel euros le en as d辿taill辿 de till
PILONI balo -2
ispeulit Mais anglais appareils guilt gens ils en anglais glory pile le vous pr竪s
... still que y pais vida Los play qu辿tej坦n Less via Leal su abuelos l叩stimaall) isa las
des audit elleguilt disons s'il souhait sous sirs vous lucius atoutes pouvait lets pas
il taille glacis Lieu daily qui les jeutaille pas bill Luc jean 辿cumait il taille Lacis just -Zuf辰lligurl zu
peut 辿lus silly mais les mes ishaute quils le aurais sans Les 辿tablis qui
des Louis de belle accueillis sell puss p竪re peut olds sects it's all辿tells peutall asplait suite
Il -12 ) pas cause subit lequel euros le en as d辿taill辿 de till
PILONI balo -2
ispeulit Mais anglais appareils guilt gens ils en anglais glory pile le vous pr竪s
... still que y pais vida Los play qu辿tej坦n Less via Leal su abuelos l叩stimaall) isa las
des audit elleguilt disons s'il souhait sous sirs vous lucius atoutes pouvait lets pas
il taille glacis Lieu daily qui les jeutaille pas bill Luc jean 辿cumait il taille Lacis just-Zuf辰lligurl zu
peut 辿lus silly mais les mes ishaute quils le aurais sans Les 辿tablis qui
des Louis de belle accueillis sell puss p竪re peut olds sects it's all辿tells peutall asplait suite
Il -12 ) pas cause subit lequel euros le en as d辿taill辿 de till
PILONI balo -2
ispeulit Mais anglais appareils guilt gens ils en anglais glory pile le vous pr竪s
... still que y pais vida Los play qu辿tej坦n Less via Leal su abuelos l叩stimaall) isa las
des audit elleguilt disons s'il souhait sous sirs vous lucius atoutes pouvait lets
INVESTIGATION OF PUEA IN COGNITIVE RADIO NETWORKS USING ENERGY DETECTION IN D...csijjournal
油
Primary User Emulation Attack (PUEA) is one of the major threats to the spectrum sensing in cognitive
radio networks. This paper studies the PUEA using energy detection that is based on the energy of the
received signal. It discusses the impact of increasing the number of attackers on the performance of
secondary user. Moreover, studying how the malicious user can emulate the Primary User (PU) signal is
made. This is the first analytical method to study PUEA under a different number of attackers. The
detection of the PUEA increases with increasing the number of attackers and decreases when changing the
channel from lognormal to Rayleigh fading.
The Uni-Bell PVC Pipe Association (PVCPA) has published the first North American industry-wide environmental product declaration (EPD) for water and sewer piping, and it has been verified by NSF Sustainability, a division of global public health organization NSF International.
Flex and rigid-flex printed circuit boards (PCBs) can be considered at the basic level some of the most complex PCBs in the industry. With that in mind, its incredibly easy to make a mistake, to leave something out, or to create a design that was doomed from the start.
Such design failures can end up leading to an eventual failure by delamination, short circuits, damage to the flex portions, and many other things. The easiest way to circumvent these is to start at the beginning, to design with preventing failure in mind rather than trying to fix existing designs to accommodate for problems.
In this webinar, we cover how to design flex and rigid-flex PCBs with failure prevention in mind to save time, money, and headaches, and what failure can look like.
For more information on our flex and rigid-flex PCB solutions, visit https://www.epectec.com/flex.
Defining the Future of Biophilic Design in Crete.pdfARENCOS
油
Biophilic design is emerging as a key approach to enhancing well-being by integrating natural elements into residential architecture. In Crete, where the landscape is rich with breathtaking sea views, lush olive groves, and dramatic mountains, biophilic design principles can be seamlessly incorporated to create healthier, more harmonious living environments.
Uses established clustering technologies for redundancy
Boosts availability and reliability of IT resources
Automatically transitions to standby instances when active resources become unavailable
Protects mission-critical software and reusable services from single points of failure
Can cover multiple geographical areas
Hosts redundant implementations of the same IT resource at each location
Relies on resource replication for monitoring defects and unavailability conditions
AI-Powered Power Converter Design Workflow.pdfAleksandr Terlo
油
introduction to embedded-converted new one
1. By: Dr. Vikas Mahor
Department of Electronics Engineering
Introduction to Embedded System
2. What is an Embedded System?
Embedded : means hidden inside so one cant see it .
System : means multiple components interfaced together
for
Doing specific task.
Embedded System : is a special-purpose computer
system designed to perform certain dedicated functions.
Functionalities : are done by dedicated HW and SW
with limited resources.
On average, a person interacts with 100s of embedded
systems on daily basis.
4. Embedded Systems - Examples
Any PC Mouse,
Keyboard, or USB
Device.
Microcontroller:
8-bit.
5. Embedded Systems - Examples
Any Disk Drive has
an embedded
Microcontroller
Any Printer has an
embedded
Microcontroller
6. Embedded Systems - Examples
Product: Creative Labs
Zen Vision:MVideo &
MP3 Player.
Microcontroller: TI
TMS320 DSP.
Canon EOS 30D Digital
Camera.
DIGIC II Image
Processor.
7. Embedded Systems - Examples
NASA's Twin Mars
Rovers.
Microprocessor:
Radiation Hardened
20MHz PowerPC From
IBM
Commercial Real-time
OS.
Software and OS was
developed during multi-
year flight to Mars and
downloaded using a
radio link.
8. Embedded Systems - Examples
Agilent Oscilloscope.
Microprocessor: X86.
OS: Windows XP.
Product: Atronic Slot
Machine.
Microprocessor: X86.
OS: Windows CE.
18. Embedded System Hardware
Microcontroller which contain :
Processor, Timers, Interrupt controller, I/O Devices, Memories, Ports, etc.
All on Single Chip Or System On Chip (SOC).
20. Microprocessor Microcontroller
Higher Clock speed Slower clock speed
CPU is stand-alone, RAM,
ROM, I/O, timer are separate
CPU,RAM, ROM, I/O and timer
are all on a single chip
Designer can decide on the amount
of ROM, RAM and I/O ports
Fix amount of on-chip ROM,
RAM, I/O ports
Expansive Cheap
General-purpose Single-purpose
High Access time for memory Low Access time for memory
Very High power Low power
21. CPU
Architectures
1) Princeton Architecture (Von Neumann Architecture) :
Between 1945 & 1951 John von Neumann set down the structure,
layout, interaction, cooperation, realization , implementation,
functionality and activity for the whole computer as a system. The Von
Neumann Architecture is characterized by: -
A memory, arithmetical-logical unit (ALU), control unit, input and
output device. etc.
All parts of a computer are connected together by Bus.
Memory and Devices are controlled by CPU .
Data can pass through bus in half duplex mode to and from CPU.
Memory is split to small cells with the same size. Their ordinal numbers
are
called address numbers.
Each time CPU fetches a program instruction it may have to perform one or
more read/write operation instruction from/to data memory space. It must
wait until these subsequent instruction are complete before it can fetch
25. CPU
Architectures
2) Harvard Architecture:
The Harvard Mark II was finished at Harvard University in 1947 . It
wasnt so modern as the computer from von Neumann team. But it
introduced a slightly different architecture. Memory for data was
separated from the memory for instruction. This concept is known as
the HarvardArchitecture :
There is no need to make the two memories share characteristics. In particular,
the word width, timing, implementation technology, and memory
address structure can differ.
The CPU can read an instruction and perform a data memory access at the same
time..
This speeds up execution time but increases the cost of more hardware
complexity.
If, for instance, every instruction run in the CPU requires an access to memory, the
computer gains nothing for increased CPU speeda problem referred to as being
"memory bound".
27. Harvard Von Neumann
Used in DSPs and other processors
found in latest embedded systems and
Mobile communication systems, audio,
speech, image processing systems
Used in conventional processo rs
found in PCs and Servers, and
embedded systems with only
control functions.
Control unit for two buses is more
complicated and more expensive
One bus is simpler for the
control unit design
The code is executed in parallel The code is executed serially
and takes more clock cycles
Avg computation speed is high Avg computation speed is low
28. CPU
Architectures
Which is the best ?
For Processors :
Von Neumann is used in Processors because, unlike MCUs, processors dont have
internal memory or peripherals and the connection to memory is through external
bus and Von Neumann is suitable because:
Cost: less buses means less cost.
Space: we dont need to waste large space of motherboard.
Processors mainly deal with only one memory, RAM which holds the
data and instructions, so only one bus will be suitable and the slow
access will be substituted by the high speed of the processor and
using the cash memory.
For Microcontroller :
Harvard architecture is used in MCU because:
Microcontroller contains everything on the chip. RAM, flash, and
peripherals and due to the small size using multiple
buses is not an issue.
Microcontroller speed is not high so multiple buses will help with
the limited speed of MCU.
29. CPU Structure
The basic elements of the CPU are:
ALU
Arithmetic & Logic Unit
Responsible for performing logic and arithmetic
calculations.
Floating-Point Unit (FPU)
performs arithmetic operations on floating point
numbers.
Registers
Registers are used to store data beside the ALU
Registers are used to transfer data to/from
memory
Registers carry the inputs of ALU, as well as,
receiving the output of the ALU.
Internal CPU Bus
It is a special bus.
It is responsible for transferring data between
registers, ALU, and system memory
Control Unit
It is responsible for organizing the actions of the CPU
It can be thought of as the heart of the CPU
30. CPU Structure
Arithmetic logic unit :
ALU is a digital circuit that performs :
Arithmetic operations :
o Add, Sub,.etc.
Logical operations :
o And, Or, Not,
etc.
Operates and stores results in general
registers
Stores operation status in flag/status
registers
Carry occurrence, overflow occurrence
31. CPU Structure
FPU ( Floating-Point Unit):
The FPU performs arithmetic operations on floating point numbers.
An FPU is complicated to design, although the IEEE 754 standard
helps to answer some of the specific questions about implementation
8086 : First computer to implement IEEE FP
Three types of the Floating-Point Data :
The half-precision floating-point format (16-bit data)
The single-precision floating-point format (32-bit data)
The double-precision floating-point format (64-bit data)
36. Instruction set architecture (ISA)
The computer ISA defines all of the programmer-visible
components and operations of the computer
memory organization
address space -- how may locations can be addressed?
addressability -- how many bits per location?
register set
how many? what size? how are they used?
instruction set
opcodes
data types
addressing modes
ISA provides all information needed for someone that
wants to write a program in machine language (or translate
from a high-level language to machine language).
37. CISC & RISC
CISC RISC
Complex Instruction Set Computer Reduced Instruction set Computer
More no of instructions Less no of instructions
Programming is easy Programming is difficult
8085,8086,Pentium PIC,AVR, ARM
Any instructions may refer memory Only LOAD/STORE refer memory
Not pipelined or less pipelined Highly pipelined
Small code sizes large code sizes
Instructions generally take more than 1
clock to execute.
Instructions execute in one clock
cycle.
Complex in Design Simple in Design
38. Memory Unit:
Memory is a part of the Any Computer System used for data storage.
Types of Memory :
Volatile Memory .
Non Volatile Memory .
39. Memory Unit:
Volatile memory :
RAM memory (Random Access Memory) :
Refers to the ability to access any memory cell directly. RAM is much
faster than ROM . It used to write and read data values while program
running .
Volatile : if you remove the power supply its contents are lost.
Any variable used in a program is allocated into RAM.
local variables, pointers, functions, recursive functions results
in using large amounts of RAM
Types Of RAM :
Dynamic RAM (DRAM)
Static RAM (SRAM)
41. Static RAM (SRAM) Dynamic RAM (DRAM)
Made From flip-flops. Made From capacitors
High cost (per bit) Low cost (per bit)
High using power Low using power
Fast Slow
Used in cache Memory Used in main memory
Large In size Low in Size
Will retain state forever Automatically discharges after
sometime, need refreshing
44. Memory Unit:
Cache Memory
Small amount of memory that is faster than RAM
Slower than registers
Built using SRAM
Range from few KB to few MB
Use by CPU to store frequently used instructions & data
Spatial & temporal locality
Use multiple levels of cache
L1 Cache Very fast, usually within CPU itself
L2 Cache Slower than L1, but faster than RAM
Today theres even L3 Cache
50. Memory Unit:
Non-Volatile memory :
ROM(Read Only Memory):
Permanent memory(Non-Volatile memory).
Used as Program Memory in Micro-Controller.
ROM generally slower than RAM.
The size of program that can be written depends on
Written upon programming the microcontroller.
Can't be written/modified at run time.
ROM Types:
Masked ROM .
OTP ROM .
UV EPROM .
EEPROM .
Flash EEPROM .
51. Memory Unit:
1-Masked ROM (MPROM) :
-Programmed by the manufacturer.
-The term maskedcomes from the manufacturing
process.
-In case of a large-scale production, the price is
very low.
52. Memory Unit:
2-OTP (One Time Programmable):
- Also called programmable ROM(PROM).
- Enables programmer to download a program into it one time only.
- Used when the firmware is stable and the product is shipping in
bulk to customers.
- If an error is detected after downloading, the only thing you can do is to
download the correct program to another chip.
53. Memory Unit:
3- UV EPROM (UV Erasable Programmable ROM)
- It enables data to be erased under strong ultraviolet light
- After a few minutes it is possible to download a new pro
gram
- the package of this microcontroller has recognizablewi
ndowon the upper side. It enables surface of the silicon
chip to be lit by an UV lamp, which has as a result that
complete program cleared and a new program download
enabled
54. Memory Unit:
4-EEPROM(Electrically Erasable Programmable ROM)
- Can be erased by exposing it to an electrical charge.
- The contents of this memory may be changed during run
time (similar to RAM),but remains permanently saved
even if the power supply is off (similar to ROM)
- EEPROM is often used to read and store values , created
during operation, which must be permanently saved.
- Acts as peripheral of microcontroller.
- Take more time in read/write access than RAM
- The max number to Write/Erase Cycles is usually100,000
but in Read is infinity
55. Memory Unit:
5-Flash EEPROM
- Invented in the 80s in the laboratories of Intel.
- Represented as the successor to the EEPROM.
- Flash is normally organized as sectors (256B - 16KB).
- Large blocks of memory erased at once, rather than one
word at a time like EEPROM , So FLASH is much faster th
an EEPROM . Take more time in read/write access than
RAM
- The max number to Write/Erase Cycles is usually10,000
but in Read is infinity
56. Memory Unit:
Type Volatile
?
Writeable
?
Erase size Max Erase
cycles
Cost per
bit
speed
SRAM Yes Yes Byte unlimited Expensive Fast
DRAM Yes Yes Byte unlimited Moderate Moderate
Masked ROM No NO -- -- Inexpensi
ve
Fast
PROM No Once -- -- Moderate Fast
EPROM No Yes Entire chip Limited(consult
datasheet(
Moderate Fast
EEPROM No Yes byte Limited(consult
datasheet(
Expensive Fast to read
slow to write
FLASH No Yes sector Limited(consult
datasheet)
Moderate Fast to read
slow to write