Introduction To Makefile
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This document provides an introduction to makefiles, including makefile syntax, the make algorithm, variables, rules, wildcards, conditionals and other features. Makefiles automate rebuilding software by defining rules and dependencies to determine the minimum commands needed. The "make" command reads the Makefile and builds targets if dependencies are newer.
![Executing shell command to assign variables $(shell command) SVN_VERSION=$(shell if test -d .svn ; then svnversion . | sed -e 's/\([1-9]*\)\([MS]\)\?:\?\([1-9]*\)[MS]\?/\1/' ; else echo unknown ; fi) VERINFO=-DSVN_VERSION="$(SVN_VERSION)" ARCH=$(shell uname -p|sed s/_/' '/|awk '{print $$2}')](https://image.slidesharecdn.com/introductiontomakefile-12679933757341-phpapp02/85/Introduction-To-Makefile-12-320.jpg)
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Introduction To Makefile
- 1. Introduction to Makefile Waqqas Jabbar
- 2. Compiling with gcc Compilation and linking in a single step gcc file1.c file2.c -o exe Compilation and linking in separate steps gcc -c file1.c gcc -c file2.c gcc file1.o file2.o -o exe
- 3. make command Makefile is the input to make command. Automate rebuilding software by determining the minimum set of commands that need to be called to do this Install program files Clean up object files Reads a file named Makefile in the directory from which it is executed
- 4. Makefile syntax Rules Target: Dependencies (tab) Command (tab) Command Target A file that is generated by a program Executable or object files The name of an action to carry out Dependencies Files that are used as inputs to create a Target Space separated list May include other targets
- 5. Makefile syntax Command Shell command If no target is specified during execution of make then the first target is used
- 6. Make algorithm Build dependencies Determine if dependency is file or action target If file by that name exist -> File Target Otherwise -> Action Target File Target Do nothing Action Target Build target dependencies
- 7. Make algorithm Check if at least one of the dependencies is newer than the target Execute Commands in that rule, if newer Definition Newer File Target: File Dependency: Check modification times Action Dependency:Check commands (in dependency rule) is executed or not Action Target: File Dependency: Always newer Action Dependency:Check commands (in dependency rule) is executed or not
- 8. Makefile variable Define Variable1 = value Usage in Commands $(Variable1) Usage in variables Variable2 = $(Variable1) Macros Variable evaluated when command is executed
- 9. Abstract Rules Defines how to build a file `*.s2' from a file `*.s1', where s1 and s2 are suffixes .s1.s2: (tab) Command (tab) Command
- 10. Punctuation $<' are the dependencies that changed causing the target to need to be rebuilt `$@' is the target `$^' are all the dependencies for the current rule
- 11. include Include other Makefiles Variables can be used
- 12. Executing shell command to assign variables $(shell command) SVN_VERSION=$(shell if test -d .svn ; then svnversion . | sed -e 's/\([1-9]*\)\([MS]\)\?:\?\([1-9]*\)[MS]\?/\1/' ; else echo unknown ; fi) VERINFO=-DSVN_VERSION="$(SVN_VERSION)" ARCH=$(shell uname -p|sed s/_/' '/|awk '{print $$2}')
- 13. Loops in command You can write loops as in shell script @for dir in $(SUBDIRS); do \ $(MAKE) -w -C $$dir $(TARGET) clean || exit 1 ; \ done
- 14. Wildcard and patsubst SRCS := $(wildcard *.cc) $(wildcard *.c) $(wildcard *.cpp) OBJS := $(patsubst %.cc, %.o,$(wildcard *.cc)) $(patsubst %.c, %.o,$(wildcard *.c)) $(patsubst %.cpp, %.o,$(wildcard *.cpp))
- 15. Environment variable checking ifeq, else,endif ifeq ($(LIB_TYPE), static) LIBEXT = a COMPILE_LIB = $(AR) -ruv $(TOP)/lib/$(LIBNAME).$(LIBEXT) $(OBJS) else LIBEXT = so COMPILE_LIB = $(CC) -fPIC -shared -Wl,-soname,$(LIBNAME).$(LIBEXT) -o $(TOP)/lib/$(LIBNAME).$(LIBEXT) $(OBJS) $(LIBS) endif
- 16. Thank you