This document discusses convolutional codes. It begins by defining a convolutional code as an error-correcting code that transforms each m-bit information symbol into an n-bit symbol, where the code rate is m/n. It then provides an example of a (2,1,8) convolutional coder with specific generator sequences. It includes diagrams of the coder circuit and trellis and discusses encoding an example message sequence. It also provides questions and answers demonstrating encoding and decoding operations using MATLAB.
The document discusses digital systems and binary numbers. It defines digital systems as systems that manipulate discrete elements of information, such as binary digits represented by the values 0 and 1. It explains how binary numbers are represented and arithmetic operations like addition, subtraction, multiplication and division are performed on binary numbers. It also discusses number base conversions between decimal, binary, octal and hexadecimal numbering systems. Finally, it covers binary complements including 1's complement, 2's complement and subtraction using complements.
This document contains solved problems related to digital communication systems. It begins by defining key elements of digital communication systems such as source coding, channel encoders/decoders, and digital modulators/demodulators. It then solves problems involving Fourier analysis of signals and generalized Fourier series. The problems cover topics like measuring performance of digital systems, classifying signals as energy or power, sketching signals, and approximating signals using generalized Fourier series.
This document proposes a concatenated coding scheme with iterative decoding for a bit-shift channel. Specifically, it considers the serial concatenation of an outer error-correcting code and an inner modulation code, possibly preceded by an accumulator. It searches for optimal encoder mappings from an iterative decoding perspective for the inner code, which has been designed to correct single bit-shift errors and have large average power. This is important for inductively coupled channels, as the receiver gets its power from the received signal and the information should maximize the power transferred.
The document discusses decoders, multiplexers, and programmable logic. It begins by explaining what decoders and multiplexers are, providing examples of 2-to-4 and 3-to-8 decoders. It then discusses how decoders and multiplexers can be used to implement arbitrary logic functions. The document also covers variations of decoders, building decoders from smaller components, and using multiplexers to efficiently implement functions in a sum of minterms form.
The International Journal of Engineering and Science (The IJES)theijes
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This document summarizes a research paper that presents a unified hybrid Reed-Solomon decoder architecture capable of correcting both burst errors and random errors/erasures. The architecture combines low-complexity algorithms for correcting burst errors and random errors. It first provides background on Reed-Solomon codes, including their encoding and standard decoding process. It then describes the proposed unified hybrid decoding architecture, which uses a reformulated inversionless algorithm for burst error correction and integrates it with standard algorithms like Berlekamp-Massey for random error correction. The architecture is the first to allow multi-mode Reed-Solomon decoding to handle different error types.
Digital systems represent information using discrete binary values of 0 and 1 rather than continuous analog values. Binary numbers use a base-2 numbering system with place values that are powers of 2. There are various number systems like decimal, binary, octal and hexadecimal that use different number bases and represent the same number in different ways. Complements are used in binary arithmetic to perform subtraction by adding the 1's or 2's complement of a number. The 1's complement is obtained by inverting all bits, while the 2's complement is obtained by inverting all bits and adding 1.
This document provides lecture notes on digital system design. It covers topics like logic simplification, combinational logic design, understanding binary and other number systems, binary operations, and Boolean algebra. The first section discusses decimal, binary, octal and hexadecimal number systems. Later sections explain binary addition, subtraction, multiplication and conversions between number bases. Signed number representations like 1's complement and 2's complement are also introduced. Finally, the document discusses Boolean algebra, logic functions, truth tables, and basic logic gates like AND and INVERTER.
The document describes experiments on generating and demodulating amplitude shift keying (ASK), phase shift keying (PSK), and frequency shift keying (FSK) signals using MATLAB.
For ASK, binary data is used to modulate a carrier signal by varying its amplitude. Demodulation recovers the data using an envelope detector. For PSK, binary data modulates the phase of a carrier signal. Demodulation correlates the signal with a reference carrier. For FSK, binary data determines the frequency of the carrier signal. Demodulation correlates the signal with two reference carriers and compares the results.
The MATLAB program for each modulation scheme generates test signals, plots the results, and recovers the data
The document describes experiments to generate and demodulate various digital modulation schemes using MATLAB, including:
- ASK modulation and demodulation using an envelope detector.
- BPSK modulation by changing the phase of a carrier signal and demodulation using correlation.
- FSK modulation by changing the frequency of a carrier signal and demodulation using correlation and subtraction.
- QPSK modulation using four phases to transmit two bits per symbol and gray encoding of the dibits.
This document discusses number systems and Boolean algebra concepts relevant to switching theory and logic design. It covers topics like number systems, binary codes, Boolean algebra theorems and properties, switching functions, logic gate simplification, and multilevel logic implementations. Various number representations are examined, including binary, octal, hexadecimal, and binary coded decimal. Conversion between number bases is demonstrated. Boolean concepts like complements, addition, and subtraction using 1's and 2's complement are also summarized.
Digital electronics is the study of electronic circuits that are used to process and control digital signals. In contrast to analog electronics, where information is represented by a continuously varying voltage, digital signals are represented by two discrete voltages or logic levels
A second important technique in error-control coding is that of convolutional coding . In this type of coding the encoder output is not in block form, but is in the form of an encoded
sequence generated from an input information sequence.
convolutional encoding is designed so that its decoding can be performed in some structured and simplified way. One of the design assumptions that simplifies decoding
is linearity of the code. For this reason, linear convolutional codes are preferred. The source alphabet is taken from a finite field or Galois field GF(q).
Convolution coding is a popular error-correcting coding method used in digital communications.
The convolution operation encodes some redundant information into the transmitted signal, thereby improving the data capacity of the channel.
Convolution Encoding with Viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.
It is simple and has good performance with low implementation cost.
The document discusses digital and analog systems. It explains that digital systems represent information as discrete values using bits, whereas analog systems represent information as continuous values. It provides examples of digital and analog signals and discusses how a continuous analog signal can be converted to a discrete digital signal through sampling and quantization. It also covers binary, octal, and hexadecimal number systems and how to convert between them. Finally, it discusses binary addition and subtraction using complement representations.
This document discusses multiplexers and demultiplexers. It defines them as devices that allow digital information from several sources to be routed onto a single line (multiplexers) or distributed to multiple output lines (demultiplexers). The key properties of multiplexers and demultiplexers are described, including the relationship between the number of inputs, outputs, and selection lines. Examples of implementing multiplexers and demultiplexers using logic gates are provided.
This document contains 25 questions related to basic digital logic gates and Boolean algebra. It covers topics like universal gates, minterms and maxterms, De Morgan's laws, Shannon expansion theorem, implementation of logic gates using other gates, parity generation, comparators and other basic concepts. Answers to each question are provided after the questions.
This document provides information about the course "Digital Electronics (WLE-102)" including details about topics, assignments, exams, textbooks, and course structure. The course covers number systems, Boolean algebra, combinational and sequential logic circuits. It is divided into four units covering number systems and codes, Boolean algebra, combinational logic circuits, and sequential logic circuits. Students will have midterm and final exams worth a total of 100 marks. Recommended textbooks are also provided.
This document discusses error coding techniques used in digital communications. It begins by explaining modulo-2 arithmetic operations that are the basis for digital coding. It then covers binary manipulation of addition and multiplication. Various error detection and correction codes are described, including cyclic redundancy check (CRC), linear block codes, and Hamming codes. Hamming codes add redundant bits to allow detection and correction of bit errors during transmission.
This document outlines the topics covered in the 21EC201 - Digital Principles and System Design course. It includes an introduction to number systems, logic gates, combinational logic circuits, Boolean algebra, truth tables and Karnaugh maps. Specific topics mentioned are binary, decimal, octal and hexadecimal number systems, logic gates like AND, OR, NAND, NOR, XOR and XNOR, arithmetic operations in binary and conversions between different number systems.
This document discusses image compression using the discrete cosine transform (DCT). It develops simple Mathematica functions to compute the 1D and 2D DCT. The 1D DCT transforms a list of real numbers into elementary frequency components. It is computed via matrix multiplication or using the discrete Fourier transform with twiddle factors. The 2D DCT applies the 1D DCT to rows and then columns, making it separable. These functions illustrate how Mathematica can be used to prototype image processing algorithms.
This document discusses image compression using the discrete cosine transform (DCT). It develops simple Mathematica functions to compute the 1D and 2D DCT. The 1D DCT transforms a list of real numbers into elementary frequency components. It is computed via matrix multiplication or using the discrete Fourier transform with twiddle factors. The 2D DCT applies the 1D DCT to rows and then columns of an image, making it separable. These functions illustrate how Mathematica can be used to prototype image processing algorithms.
This document provides lecture notes on digital system design. It covers topics like logic simplification, combinational logic design, understanding binary and other number systems, binary operations, and Boolean algebra. The first section discusses decimal, binary, octal and hexadecimal number systems. Later sections explain binary addition, subtraction, multiplication and conversions between number bases. Signed number representations like 1's complement and 2's complement are also introduced. Finally, the document discusses Boolean algebra, logic functions, truth tables, and basic logic gates like AND and INVERTER.
The document describes experiments on generating and demodulating amplitude shift keying (ASK), phase shift keying (PSK), and frequency shift keying (FSK) signals using MATLAB.
For ASK, binary data is used to modulate a carrier signal by varying its amplitude. Demodulation recovers the data using an envelope detector. For PSK, binary data modulates the phase of a carrier signal. Demodulation correlates the signal with a reference carrier. For FSK, binary data determines the frequency of the carrier signal. Demodulation correlates the signal with two reference carriers and compares the results.
The MATLAB program for each modulation scheme generates test signals, plots the results, and recovers the data
The document describes experiments to generate and demodulate various digital modulation schemes using MATLAB, including:
- ASK modulation and demodulation using an envelope detector.
- BPSK modulation by changing the phase of a carrier signal and demodulation using correlation.
- FSK modulation by changing the frequency of a carrier signal and demodulation using correlation and subtraction.
- QPSK modulation using four phases to transmit two bits per symbol and gray encoding of the dibits.
This document discusses number systems and Boolean algebra concepts relevant to switching theory and logic design. It covers topics like number systems, binary codes, Boolean algebra theorems and properties, switching functions, logic gate simplification, and multilevel logic implementations. Various number representations are examined, including binary, octal, hexadecimal, and binary coded decimal. Conversion between number bases is demonstrated. Boolean concepts like complements, addition, and subtraction using 1's and 2's complement are also summarized.
Digital electronics is the study of electronic circuits that are used to process and control digital signals. In contrast to analog electronics, where information is represented by a continuously varying voltage, digital signals are represented by two discrete voltages or logic levels
A second important technique in error-control coding is that of convolutional coding . In this type of coding the encoder output is not in block form, but is in the form of an encoded
sequence generated from an input information sequence.
convolutional encoding is designed so that its decoding can be performed in some structured and simplified way. One of the design assumptions that simplifies decoding
is linearity of the code. For this reason, linear convolutional codes are preferred. The source alphabet is taken from a finite field or Galois field GF(q).
Convolution coding is a popular error-correcting coding method used in digital communications.
The convolution operation encodes some redundant information into the transmitted signal, thereby improving the data capacity of the channel.
Convolution Encoding with Viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.
It is simple and has good performance with low implementation cost.
The document discusses digital and analog systems. It explains that digital systems represent information as discrete values using bits, whereas analog systems represent information as continuous values. It provides examples of digital and analog signals and discusses how a continuous analog signal can be converted to a discrete digital signal through sampling and quantization. It also covers binary, octal, and hexadecimal number systems and how to convert between them. Finally, it discusses binary addition and subtraction using complement representations.
This document discusses multiplexers and demultiplexers. It defines them as devices that allow digital information from several sources to be routed onto a single line (multiplexers) or distributed to multiple output lines (demultiplexers). The key properties of multiplexers and demultiplexers are described, including the relationship between the number of inputs, outputs, and selection lines. Examples of implementing multiplexers and demultiplexers using logic gates are provided.
This document contains 25 questions related to basic digital logic gates and Boolean algebra. It covers topics like universal gates, minterms and maxterms, De Morgan's laws, Shannon expansion theorem, implementation of logic gates using other gates, parity generation, comparators and other basic concepts. Answers to each question are provided after the questions.
This document provides information about the course "Digital Electronics (WLE-102)" including details about topics, assignments, exams, textbooks, and course structure. The course covers number systems, Boolean algebra, combinational and sequential logic circuits. It is divided into four units covering number systems and codes, Boolean algebra, combinational logic circuits, and sequential logic circuits. Students will have midterm and final exams worth a total of 100 marks. Recommended textbooks are also provided.
This document discusses error coding techniques used in digital communications. It begins by explaining modulo-2 arithmetic operations that are the basis for digital coding. It then covers binary manipulation of addition and multiplication. Various error detection and correction codes are described, including cyclic redundancy check (CRC), linear block codes, and Hamming codes. Hamming codes add redundant bits to allow detection and correction of bit errors during transmission.
This document outlines the topics covered in the 21EC201 - Digital Principles and System Design course. It includes an introduction to number systems, logic gates, combinational logic circuits, Boolean algebra, truth tables and Karnaugh maps. Specific topics mentioned are binary, decimal, octal and hexadecimal number systems, logic gates like AND, OR, NAND, NOR, XOR and XNOR, arithmetic operations in binary and conversions between different number systems.
This document discusses image compression using the discrete cosine transform (DCT). It develops simple Mathematica functions to compute the 1D and 2D DCT. The 1D DCT transforms a list of real numbers into elementary frequency components. It is computed via matrix multiplication or using the discrete Fourier transform with twiddle factors. The 2D DCT applies the 1D DCT to rows and then columns, making it separable. These functions illustrate how Mathematica can be used to prototype image processing algorithms.
This document discusses image compression using the discrete cosine transform (DCT). It develops simple Mathematica functions to compute the 1D and 2D DCT. The 1D DCT transforms a list of real numbers into elementary frequency components. It is computed via matrix multiplication or using the discrete Fourier transform with twiddle factors. The 2D DCT applies the 1D DCT to rows and then columns of an image, making it separable. These functions illustrate how Mathematica can be used to prototype image processing algorithms.
This presentation provides an in-depth analysis of structural quality control in the KRP 401600 section of the Copper Processing Plant-3 (MOF-3) in Uzbekistan. As a Structural QA/QC Inspector, I have identified critical welding defects, alignment issues, bolting problems, and joint fit-up concerns.
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✔ Common Structural Defects – Welding porosity, misalignment, bolting errors, and more.
✔ Root Cause Analysis – Understanding why these defects occur.
✔ Corrective & Preventive Actions – Effective solutions to improve quality.
✔ Team Responsibilities – Roles of supervisors, welders, fitters, and QC inspectors.
✔ Inspection & Quality Control Enhancements – Advanced techniques for defect detection.
📌 Applicable Standards: GOST, KMK, SNK – Ensuring compliance with international quality benchmarks.
🚀 This presentation is a must-watch for:
✅ QA/QC Inspectors, Structural Engineers, Welding Inspectors, and Project Managers in the construction & oil & gas industries.
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Lecture -3 Cold water supply system.pptxrabiaatif2
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The presentation on Cold Water Supply explored the fundamental principles of water distribution in buildings. It covered sources of cold water, including municipal supply, wells, and rainwater harvesting. Key components such as storage tanks, pipes, valves, and pumps were discussed for efficient water delivery. Various distribution systems, including direct and indirect supply methods, were analyzed for residential and commercial applications. The presentation emphasized water quality, pressure regulation, and contamination prevention. Common issues like pipe corrosion, leaks, and pressure drops were addressed along with maintenance strategies. Diagrams and case studies illustrated system layouts and best practices for optimal performance.
1. In telecommunication, a convolutional code is a type of error-
correcting code in which each m-bit information symbol (each m-bit-
string) to be encoded is transformed into an n-bit symbol, where m/n is
the code rate (n ≥ m).
Convolutional code
1
2. Fig. below shows a (2,1,8) coder with g1 = (1 1 1 1 0 1 0 1 1) and
g2 = (1 0 1 1 1 0 0 0 1) where g1 and g2 are generator sequences
C
Information
frame S
M3 M4 M5 M6 M7 M8
C2
+
+
M9
C1
M2
M1
Let the message sequence, S = 1010000100000101
The channel frame would be input sequence with m = 8 tail bits of ‘0’
2
(l, k, r)
l=no. of output terminal
K=no. of input terminal
r=no. of memory cells
4. C = 11 10 00 01 10 01 01 00 00 00 00 00 11 10 01 11 00 10 11 10 00
11 10 11
Length of C is 48 bits
The rate of the coder is n/m=16/48=1/3
Length of code sequence is determined using the relation,
L = l(S+r) = 2(16+8) = 48
; where l is the number of output; r is the number of shift register and
S is the length of message string.
4
5. Q: Design a convolution coder (2,1,2) with g1 = 1 1 1 and g2 = 1 0 1 with M = 2.
Determine output for message sequence, S = 1 0 0 1 1
Ans:
Here is S = 1 0 0 1 1
The channel frame would be input sequence with m = 2 tail bits of ‘0’ frame,
M = 1 0 0 1 1 0 0
C1 = M1+M2+M3
C2 = M1+M3
Here sum of C1 and C2 are X-OR sum
The circuit diagram of the coder is shown in fig. below.
M3
M2
M1
C1
S
C2
m1
m2
+
+
Clock M M1 M2 M3 C1 C2
1 1 1 0 0 1 1
2 0 0 1 0 1 0
3 0 0 0 1 1 1
4 1 1 0 0 1 1
5 1 1 1 0 0 1
6 0 0 1 1 0 1
7 0 0 0 1 1 1
5
6. C = 11 10 11 11 01 01 11 i.e. the length of codeword is14 bits.
Length of code sequence
L = l (S+r)
= 2(5+2) = 14
6
8. 8
Q1. A convolution coder with g1 = 1 1 1 and g2 = 1 0 1 with m =
2. Determine output code sequence for S = 10011 using Matlab.
Ans. Here d1 = g1*S and d2 = g2*S
g1=[1 1 1];
g2=[1 0 1];
S=[1 0 0 1 1];
d1=rem(conv(g1,S),2); %Modulo-2 addition
d2=rem(conv(g2,S),2);% %Modulo-2 addition
d1 = 1 1 1 1 0 0 1
d2 = 1 0 1 1 1 1 1
9. 9
Q2. A convolution coder with g1 = 1 0 1 1 and g2 = 1 1 1 1 with
m = 2. Determine output code sequence for S = 1 0 1 1 1 using
Matlab.
g1=[1 0 1 1];
g2=[1 1 1 1];
S=[1 0 1 1 1];
d1=rem(conv(g1,S),2); %Modulo-2 addition
d2=rem(conv(g2,S),2);% %Modulo-2 addition
d1 = 1 0 0 0 0 0 0 1
d2 = 1 1 0 1 1 1 0 1
10. Graphical Presentation of Convoluational Coder
A convolutional coder can be expressed in three graphical form
a) code tree
b) state diagram
c) trellis diagram
10
12. b) state diagram
Let us consider the convolutional coder of the fig.below; where content of the two
memory units m1 and m2 can take any one of the four state 00, 01, 10 and 11.
M3
M2
M1
C1
S
C2
m1
m2
+
+
1
0
m1 m2
0 0
m1 m2
0 1
m1 m2
1 1
m1 m2
1 0
11
11
01
01 10
00
00
10
12
13. Let us consider a trellis between k and (k+1)th clock shown in fig. below
0
1
00
01
10
11
00
11
11
00
10
01 01
10
13
c) Trellis diagram
1
0
m1 m2
0 0
m1 m2
0 1
m1 m2
1 1
m1 m2
1 0
11
11
01
01 10
00
00
10
16. MATLAB
Determine encoded data of the convolutional encoder of fig. 8.1,
where the message sequence is, m = [1 0 0 1 1 0 0]. Here the last two
zeros of m are for two FF (memory cell) of the encoder; not the part of
the message sequence.
m
C
M1 M2
+
+
m = [1 0 0 1 1 0 0];
t = poly2trellis( 3, [7,5] );
%Formation of the sequential circuit of fig
%length of generator sequence is 3
%generator g1 = 111 = 7 and g2 = 101 = 5
c = convenc(m, t)
The result of above code is,
c = 1 1 1 0 1 1 1 1 0 1 0 1 1 1
16
18. Let us decode c by Viterbi algorithm.
tb=1% traceback depth
v=vitdec(c, t, tb, 'cont', 'hard')
Above code gives one bit delayed version of message vector, m.
v =
0 1 0 0 1 1 0
Determine bit error of above encoder and decoder system.
[b,r]=biterr(v(tb+1:end), m(1:end-tb))
b = 0
r = 0
18
19. 19
trellis = poly2trellis( 3, [7,5] );
spect = distspec(trellis,4)
berub = bercoding(1:10,'conv','hard',2/3,spect); % BER bound
berfit(1:10,berub); ylabel('Upper Bound on BER'); % Plot.
G=2; %channel gain
for SNR=1:12
t = poly2trellis([4 3],[4 5 17;7 4 2]); % Define trellis.
tb = 2; % Traceback length for decoding
% Create a ConvolutionalEncoder System object
hConvEnc = comm.ConvolutionalEncoder(t);
% Create a ViterbiDecoder System object
hVitDec = comm.ViterbiDecoder(t, 'InputFormat', 'hard', ...
'TracebackDepth', tb, 'TerminationMethod', 'Truncated');
data=randi(2,200000,1)-1; %random binary bits
code = step(hConvEnc, data); % Encode a string of ones.
decoded = step(hVitDec, awgn(G*code, SNR)); % Decode under awgn.
[a,b]=symerr(decoded, data);
e(SNR)=b;
end
semilogy(1:12,e, '*-')
20. 20
t = poly2trellis([4 3],[4 5 17;7 4 2]); % Define trellis.
tb = 2; % Traceback length for decoding
% Create a ConvolutionalEncoder System object
hConvEnc = comm.ConvolutionalEncoder(t);
% Create a ViterbiDecoder System object
hVitDec = comm.ViterbiDecoder(t, 'InputFormat', 'hard', ...
'TracebackDepth', tb, 'TerminationMethod', 'Truncated');
data=randi(2,20000,1)-1; %random binary bits
code = step(hConvEnc, data); % Encode a string of ones.
decoded = step(hVitDec, code+randerr(length(code),1,[0 1;0.9 0.1]));
% randerr produces bit string randomly with pr of 0 of 96% and 1 of 4%
% Decode under awgn.
[a,b]=symerr(decoded, data)