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Logic Synthesis with
SYNOPSYS DESIGN COMPILER

Presenters:
Muhammad Umer Kakli
Muhammad Naeem Tayyab

Agenda
ASIC Design Flow
Logic Synthesis
Logic Synthesis Process
Design Compiler
DC Flow
 Synthesis Steps
Getting Started with DC
Q & A

ASIC Design Flow

Dr. Osman Hasan’s Lectures on ASIC Design Methodology, SEECS, NUST, 2011

Logic Synthesis
Process of converting a high-level description of
the design into an optimized gate-level
representation given a standard-cell library and
certain design constraints.

Logic Synthesis Process
HDL
Translation to Data Structure
Optimization
Logic Mapping
Reports

Image Courtesy: www.docstoc.com/docs/27375300/Logic-Synthesis-with-Synopsys

Logic Synthesis Tools
“Design Compiler” by Synopsys
“Encounter RTL Compiler” by Cadence
“TalusDesign” by Magma Design Automation

The Design Compiler
It is the core of the Synopsys synthesis software
products. It includes tools that synthesis the HDL
designs into optimized technology-dependent,
gate level designs. It can optimize for speed, area
and power.
Interfaces
- Design Vision
- dc_shell

Flow through Design Compiler

http://wenku./view/32dd1c7ca26925c52cc5bf61.html

Logic Synthesis Steps
Develop HDL Files
Specify Libraries
Read Design
Define Design Environment
Set Design Constraint
Optimize the Design
Analyze and Resolve the Design Problems

Getting Started
Initialization
- $ source /share/tktprog/synopsys/syn-2007.03-SP2/syn.sh

Project Setup
Directory Structure

Project Setup (Contd.)
Setup File
- .synposys_dc.setup

Invoking Design Vision
 $ design_vision

Example
4-bit Ripple Carry Adder

Checking Libraries
File -> setup

 get_design_lib_path WORK
- ./SYN/WORK/ library

Reading Design
Load design into Design Compiler Memory. It
consists of two operations
- Analyzing design: Top level of Hierarchy
- Elaborating design: Lower level block associated

Reading Design (Analyze)
File->analyze

 analyze -library WORK -format vhdl {./SRC/ha.vhd
./SRC/fa.vhd ./SRC/rca.vhd ./SRC/adder.vhd}

Reading Design (Elaborate)
File->elaborate

 elaborate ADDER -architecture RTL -library WORK -
parameters"N=4"

Checking Design Structure
Using Hierarchy Browser

Checking Design Structure (Contd.)
Creating Design Schematic

Look for Multiple Designs
 check_design -multiple_designs

Saving Design
File->Save As

 write_file -format ddc -hierarchy -output
./SYN/DDC/adder_N4_elab.ddc

Setting Constraints
Create or modify a clock
Set input and output delays
 Set drive strengths
 Set loads
Select operating conditions
 Choose a wire load model

Setting Constraints
Menubar->Attribute

Setting Constraints (Contd.)
 create_clock -name "clk" -period 4 -waveform {0 2} {clk}
set_clock_uncertainty 0.1 clk
set_clock_latency 0.2 clk
set_clock_transition 0.1 clk
set_dont_touch_network clk

 set_driving_cell -library umcl18g212t3_tc_180V_25C -lib_cell
HDDFFPB1 -pin Q [get_ports a]
set_driving_cell -library umcl18g212t3_tc_180V_25C -lib_cell HDINVD1
-pin Z [get_ports b] set_load [load_of
umcl18g212t3_tc_180V_25C/HDDFFPB1/D] [get_ports s]

 set_input_delay 0.67 [get_ports b] -clock clk
set_output_delay 0.5 [get_ports s] -clock clk

 set_max_area 1000

Optimizing the Design
Design->Compile

 compile

Design Analysis and Reporting
Report Design (Design->Report Design)
Report Wire Loads (Design->Report Wire Loads)
Report Ports (Design-> Report Ports )
Report Clocks (Design-> Report Clocks )
Report Area (Design-> Report Area )
Report Power (Design-> Report Power )

Design Analysis and Reporting (Contd.)
 report_constraint -all_violators
 report_area > ./SYN/RPT/report_area_default.txt

Critical Path
Highlight->Critical Path

Critical Path (Full Path at Glance)
Schematic -> New Path Schematic View

Synthesis Results
Noncombinational Area/µm² 274.17
Combinational Area/µm² 367.71
Total Area/µm² 641.89
Critical Path Slack/ns 1.69
Total Negative Slack/ns 0.0
Levels of Logic 9
Leaf Cell Count 26

Are you fine with results?
SAVE the Synthesized design.
 write_file -format ddc -hierarchy –output Compiled Design
./SYN/DDC/adder_N4_default_compiled.ddc Database
 write_file -format verilog -hierarchy -output
Verilog/VHDL
./SYN/NETLIST/adder_N4_default_compiled.v
Netlist

References
 http://www.tkt.cs.tut.fi/tools/public/tutorials/synopsys/design_co
mpiler/gsdc.html#read_design

 http://www.engr.sjsu.edu/tle/271_DV_tut.pdf

 http://www.ece.wisc.edu/~morrow/ECE551/tutorials/DesignVision
Tutorial_f07.pdf

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Logic synthesis with synopsys design compiler

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Logic synthesis with synopsys design compiler