ºÝºÝߣ

ºÝºÝߣShare a Scribd company logo

Mesa_Yogananda_ASIC_FPGA_Verification

•Download as DOC, PDF•
•
Yogananda Mesa
Yogananda Mesa

Yogananda Mesa is applying for an ASIC Verification Engineer role. He has 1 year of experience as a Verification Engineer using SystemVerilog and UVM methodologies. His experience includes RTL design and verification, IP verification, assertion-based verification, and coverage-driven verification. He is proficient in Verilog, SystemVerilog, UVM, C/C++, Java, and protocols like AMBA. His projects include verifying an APB protocol design, designing and verifying a dual-port RAM FIFO, and designing and verifying an arbiter. He completed an M.Tech in VLSI System Design.

1 of 3
Download to read offline
Name Yogananda Mesa Proposed Role ASIC Verification Engineer Experience Summary I am working as a Verification Engineer in Tata Consultancy Services and have an experience of 1 year in IP level Verification using SV with methodologies UVM. I have hands on experience in RTL Design and Verification. I intend to build a career in the area of VLSI by working on the emerging technologies related to this field and further strengthening my skill sets. • Experience in front-end Verification using System Verilog, UVM and RTL Design. • Expertise in verification tool Synopsys VCS. • Good in Assertion based verification. • Good in Constraint based and Coverage Driven Verification. • Exposure to AMBA protocols. • Good in Core java, C++. • Strong Analytical, Coding and Debugging skills • Good Team player Skill Summary Domain Design and verification Engineer Education M.Tech in VLSI System Design Operating Systems Linux, Windows Languages Verilog, System Verilog, UVM, C, C++, core Java, Perl Protocols AMBA APB,AXI,AHB Tools Synopsys VCS (simulation and verification) Project Summary Aug 2016 – Till date Architecture implementation and Test plan of Packet Processor. Receive the input packet stream and route the packets to the other terminal devices according to the input configuration by adding the Headers and CRC and verify the CRC from the incoming packets within the Packet Processor. Detection of the errors in the incoming packets and adding the error signal to the respective and correct them. Responsibilities: • Design of Protocol checker and corrector. • Design of Header and CRC insertion blocks according to the Configuration. • Implementation of the verification test plan. May 2016-June 2016 Design and Verification of APB Protocol
Design and verify APB protocol with FIFO as Master and SRAM as a Slave. The Advance Peripheral Bus(APB) is part of the AMBA hierarchy of buses and is optimized for minimal power consumption and reduced interface complexity. Responsibilities: • Understand the specifications and working of APB protocol • Designed the APB slave SRAM and verified using Verilog test bench • Designed the APB master and FIFO • Verified the Design using UVM • Implemented the Assertions to check functionality of the Design • Implemented the constraints for getting required stimulus generation • Implemented coverage class for checking code coverage April 2016 – May 2016 Design and verification of Dual port Ram based FIFO A RAM based system having a dual port first in, first out (FIFO) which performs read operations in synchronized with a read clock signal and write operations in synchronized with a write clock signal. The read clock signal is asynchronous with respect to the write clock signal. Responsibilities: • Designing of Dual port Ram based FIFO using Verilog • Verified the Design using System Verilog and UVM • Written the Assertions to check functionality • Implemented the Coverage class for checking code coverage February 2016 – March 2016 Design and Verification of Arbiter Design and verify the multi-request multi-grant arbiter with round robin logic using Verilog and System Verilog. Responsibilities: • Designing of Arbiter using Verilog • Verified the Design using System Verilog • Written the Assertions to check functionality M.Tech project July 2014 - Oct 2015 Design and verification of 7-segment display with FIFO read-out using UVM. System Verilog is an IEEE standard Verification language. The library and package oriented feature provide an efficient way of writing test benches. The Universal Verification Methodology (UVM) Class Library provides the building blocks needed to quickly develop reusable and well-
constructed verification components and test environments using System Verilog. In this project I have designed and developed testing environment using system Verilog implementation of UVM for 7-SEGMENT DISPLAY WITH FIFO READ-OUT which reads the data from Asynchronous FIFO. Responsibilities: • Our work introduces an automated stimulus generating testing environment for the design and checks the functionality of the 7-SEGMENT DISPLAY WITH FIFO READ-OUT. • Written the Assertions for testing functionality • Written the Coverage to find the code coverage and got 98% of code coverage Personal Details Name : Yogananda Mesa Date of birth : 02-06-1990 Mail id : mesa.yogananda@gmail.com Contact : +91 9652301083

More Related Content

Mesa_Yogananda_ASIC_FPGA_Verification

  • 1. Name Yogananda Mesa Proposed Role ASIC Verification Engineer Experience Summary I am working as a Verification Engineer in Tata Consultancy Services and have an experience of 1 year in IP level Verification using SV with methodologies UVM. I have hands on experience in RTL Design and Verification. I intend to build a career in the area of VLSI by working on the emerging technologies related to this field and further strengthening my skill sets. • Experience in front-end Verification using System Verilog, UVM and RTL Design. • Expertise in verification tool Synopsys VCS. • Good in Assertion based verification. • Good in Constraint based and Coverage Driven Verification. • Exposure to AMBA protocols. • Good in Core java, C++. • Strong Analytical, Coding and Debugging skills • Good Team player Skill Summary Domain Design and verification Engineer Education M.Tech in VLSI System Design Operating Systems Linux, Windows Languages Verilog, System Verilog, UVM, C, C++, core Java, Perl Protocols AMBA APB,AXI,AHB Tools Synopsys VCS (simulation and verification) Project Summary Aug 2016 – Till date Architecture implementation and Test plan of Packet Processor. Receive the input packet stream and route the packets to the other terminal devices according to the input configuration by adding the Headers and CRC and verify the CRC from the incoming packets within the Packet Processor. Detection of the errors in the incoming packets and adding the error signal to the respective and correct them. Responsibilities: • Design of Protocol checker and corrector. • Design of Header and CRC insertion blocks according to the Configuration. • Implementation of the verification test plan. May 2016-June 2016 Design and Verification of APB Protocol
  • 2. Design and verify APB protocol with FIFO as Master and SRAM as a Slave. The Advance Peripheral Bus(APB) is part of the AMBA hierarchy of buses and is optimized for minimal power consumption and reduced interface complexity. Responsibilities: • Understand the specifications and working of APB protocol • Designed the APB slave SRAM and verified using Verilog test bench • Designed the APB master and FIFO • Verified the Design using UVM • Implemented the Assertions to check functionality of the Design • Implemented the constraints for getting required stimulus generation • Implemented coverage class for checking code coverage April 2016 – May 2016 Design and verification of Dual port Ram based FIFO A RAM based system having a dual port first in, first out (FIFO) which performs read operations in synchronized with a read clock signal and write operations in synchronized with a write clock signal. The read clock signal is asynchronous with respect to the write clock signal. Responsibilities: • Designing of Dual port Ram based FIFO using Verilog • Verified the Design using System Verilog and UVM • Written the Assertions to check functionality • Implemented the Coverage class for checking code coverage February 2016 – March 2016 Design and Verification of Arbiter Design and verify the multi-request multi-grant arbiter with round robin logic using Verilog and System Verilog. Responsibilities: • Designing of Arbiter using Verilog • Verified the Design using System Verilog • Written the Assertions to check functionality M.Tech project July 2014 - Oct 2015 Design and verification of 7-segment display with FIFO read-out using UVM. System Verilog is an IEEE standard Verification language. The library and package oriented feature provide an efficient way of writing test benches. The Universal Verification Methodology (UVM) Class Library provides the building blocks needed to quickly develop reusable and well-
  • 3. constructed verification components and test environments using System Verilog. In this project I have designed and developed testing environment using system Verilog implementation of UVM for 7-SEGMENT DISPLAY WITH FIFO READ-OUT which reads the data from Asynchronous FIFO. Responsibilities: • Our work introduces an automated stimulus generating testing environment for the design and checks the functionality of the 7-SEGMENT DISPLAY WITH FIFO READ-OUT. • Written the Assertions for testing functionality • Written the Coverage to find the code coverage and got 98% of code coverage Personal Details Name : Yogananda Mesa Date of birth : 02-06-1990 Mail id : mesa.yogananda@gmail.com Contact : +91 9652301083