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pipelining

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Sadaf Rasheed

The document discusses parallel processing and pipelining. It defines parallel processing as performing concurrent data processing to achieve faster execution. This can be done by having multiple ALUs that can execute instructions simultaneously. The document then discusses Flynn's classification of computer architectures based on instruction and data streams. It describes single instruction single data (SISD), multiple instruction single data (MISD), and multiple instruction multiple data (MIMD) architectures. The document then defines pipelining as decomposing processes into sub-operations that flow through pipeline stages. It provides examples of arithmetic and instruction pipelines, describing the stages in each.

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pipelining
Presented By Saifullah Abbasi 2K15-CSE-76 Abdul Jabbar Tunio 2K15-CSE-04
Presentation Topic 1. Parallel processing 2. Pipelining 3. Pipeline categories a) Arithmetic pipeline b) Instruction pipeline
Parallel Processing A Parallel Processing system is able to perform concurrent data processing to achieve faster execution time.
Parallel Processing Example: While an instruction is being executed in the ALU, the next instruction can be read from memory. The system may have two or more ALUs and be able to execute two or more instructions at the same time. So the purpose of parallel processing is to speedup the computer processing capabilities.
Parallel Processing Parallel Processing can be viewed from various level of complexity. 1. Lowest level: We distinguish between parallel and serial operations by the type of Registers used. 2. High level: Parallel Processing at higher level of complexity can be achieved by having an multiplicity of functional units the perform different operations simultaneously.
pipelining
FLYNNS CLASSIFICATION Flynns Classification of computer was based on new concepts which is Instruction Stream and Data Stream for parallel computing.
FLYNNS CLASSIFICATION Instruction Stream & Data Stream The term Stream refers to a sequence flow of either instruction or data operated on by the computer. Instruction Stream: In the complete cycle of instruction execution, a flow of instruction from main memory to the CPU is established, this flow of instruction is called IS. Data Stream: Flow of operands between processor and memory bi-directionally. The flow of operands is called DS.
CPU Main Memory Instruction Stream Data Stream
SINGLE INSTRUCTION & SINGLE DATA STREAM (SISD) In this organization, Sequential execution by instruction is performed by one CPU containing a single processing element (PE), i.e. ALU under one control unit. IS=DS=1 Processing unit Control Unit ALU Main MemoryIS DS IS
MULTIPLE INSTRUCTION & SINGLE DATA STREAM (MISD) In MISD multiple processing elements are organized under the control of multiple control unit. Each CU is handling one instruction stream and processed through its corresponding processing element. But each processing element is processing only a single data stream at a time.
MULTIPLE INSTRUCTION AND SINGLE DATA STREAM (MISD) In MISD multiple CUs and Multiple Processing Elements are organized in this classification.
MUTIPLE INSTRUCTION & MULTIPLE DATA STREAM (MIMD) In this Multiple Instruction Streams operate on Multiple Data Stream. Therefore handling Multiple Instruction Streams, Multiple Control Units & Multiple Processing elements are organized. Such that Multiple Processing Elements are handling Multiple Data Stream from main memory.
IS>1 DS>1
Pipelining Pipelining is a technique of decomposing sequence process into sub-operations, collection of processing segment through which binary information flows. A Pipeline is series of stages, where some work is done at each stage. The work is not finished until it has passed through all stages.
Pipelining Pipelining is an speed up technique where multiple instruction are overlapped in execution on a processor. Pipeline structure is to imagine that each segment consist of an input register followed by combinational circuit. The Register hold the data and combinational circuit performs the operations.
pipelining
Example Multiply and Add operation: Ai*Bi +Ci 3 Sub operation Segment
How Pipeline Works? The pipeline is divided into segments and each segment can execute it operation concurrently with the other segments. Once a segment completes an operations, it passes the result to the next segment in the pipeline and fetches the next operations from the preceding segment.
Idea of pipelining in computer The processor execute the program by fetching and executing instructions. One after the other. Let Fi and Ei refer to the fetch and execute steps for instruction Ii
Use the Idea of Pipelining in a Computer
Advantages/Disadvantage s Advantages: More efficient use of processor Quicker time of execution of large number of instructions
Arithmetic Pipeline Pipeline arithmetic units are usually found in very high speed computers. They are used to implement floating point operations. We will now discuss the pipeline unit for the floating point addition and subtraction.
Arithmetic Pipeline The inputs to floating point adder pipeline are two normalized floating point numbers. A and B are mantissas and a and b are the exponents. The floating point addition and subtraction can be performed in four segments.
Arithmetic Pipeline The sub-operation performed in each segments are: Compare the exponents Align the mantissas Add or subtract the mantissas Normalize the result
Compare Exponent: The exponent are compared by subtracting them to determine their difference. Align the mantissas: The exponent difference determines how many times the mantissas associated with smaller exponent must be shifted to the right.
Normalize the result Overflow: Shifted right and exponent increments by one. Underflow: Shifted to left and number must be subtracted from exponent.
pipelining
pipelining
Instruction Pipeline Pipeline processing can occur not only in the data stream but in the instruction stream as well. An instruction pipeline reads consecutive instruction from memory while previous instruction are being executed in other segments. This caused the instruction fetch and execute segments to overlap and perform simultaneous operation.
Machine Cycle
Instruction Pipeline Instruction execution process lends itself naturally to pipelining overlap the subtasks of instruction fetch, decode and execute Instruction pipeline has six operations, Fetch instruction (FI) Decode instruction (DI) Calculate operands (CO) Fetch operands (FO) Execute instructions (EI) Write result (WR) Overlap these operations
Instructions Fetch The IF stage is responsible for obtaining the requested instruction from memory. The instruction and the program counter are stored in the register as temporary storage. Decode Instruction The DI stage is responsible for decoding the instruction and sending out the various control lines to the other parts of the processor.
Calculate Operands The CO stage is where any calculations are performed. The main component in this stage is the ALU. The ALU is made up of arithmetic, logic and capabilities. Fetch Operands and Execute Instruction The FO and EI stages are responsible for storing and loading values to and from memory. They also responsible for input and output from the processor respectively.
Write Operands The WO stage is responsible for writing the result of a calculation, memory access or input into the register file.
Timing Diagram for Instruction Pipeline Operation
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pipelining

  • 2. Presented By Saifullah Abbasi 2K15-CSE-76 Abdul Jabbar Tunio 2K15-CSE-04
  • 3. Presentation Topic 1. Parallel processing 2. Pipelining 3. Pipeline categories a) Arithmetic pipeline b) Instruction pipeline
  • 4. Parallel Processing A Parallel Processing system is able to perform concurrent data processing to achieve faster execution time.
  • 5. Parallel Processing Example: While an instruction is being executed in the ALU, the next instruction can be read from memory. The system may have two or more ALUs and be able to execute two or more instructions at the same time. So the purpose of parallel processing is to speedup the computer processing capabilities.
  • 6. Parallel Processing Parallel Processing can be viewed from various level of complexity. 1. Lowest level: We distinguish between parallel and serial operations by the type of Registers used. 2. High level: Parallel Processing at higher level of complexity can be achieved by having an multiplicity of functional units the perform different operations simultaneously.
  • 8. FLYNNS CLASSIFICATION Flynns Classification of computer was based on new concepts which is Instruction Stream and Data Stream for parallel computing.
  • 9. FLYNNS CLASSIFICATION Instruction Stream & Data Stream The term Stream refers to a sequence flow of either instruction or data operated on by the computer. Instruction Stream: In the complete cycle of instruction execution, a flow of instruction from main memory to the CPU is established, this flow of instruction is called IS. Data Stream: Flow of operands between processor and memory bi-directionally. The flow of operands is called DS.
  • 11. SINGLE INSTRUCTION & SINGLE DATA STREAM (SISD) In this organization, Sequential execution by instruction is performed by one CPU containing a single processing element (PE), i.e. ALU under one control unit. IS=DS=1 Processing unit Control Unit ALU Main MemoryIS DS IS
  • 12. MULTIPLE INSTRUCTION & SINGLE DATA STREAM (MISD) In MISD multiple processing elements are organized under the control of multiple control unit. Each CU is handling one instruction stream and processed through its corresponding processing element. But each processing element is processing only a single data stream at a time.
  • 13. MULTIPLE INSTRUCTION AND SINGLE DATA STREAM (MISD) In MISD multiple CUs and Multiple Processing Elements are organized in this classification.
  • 14. MUTIPLE INSTRUCTION & MULTIPLE DATA STREAM (MIMD) In this Multiple Instruction Streams operate on Multiple Data Stream. Therefore handling Multiple Instruction Streams, Multiple Control Units & Multiple Processing elements are organized. Such that Multiple Processing Elements are handling Multiple Data Stream from main memory.
  • 16. Pipelining Pipelining is a technique of decomposing sequence process into sub-operations, collection of processing segment through which binary information flows. A Pipeline is series of stages, where some work is done at each stage. The work is not finished until it has passed through all stages.
  • 17. Pipelining Pipelining is an speed up technique where multiple instruction are overlapped in execution on a processor. Pipeline structure is to imagine that each segment consist of an input register followed by combinational circuit. The Register hold the data and combinational circuit performs the operations.
  • 19. Example Multiply and Add operation: Ai*Bi +Ci 3 Sub operation Segment
  • 20. How Pipeline Works? The pipeline is divided into segments and each segment can execute it operation concurrently with the other segments. Once a segment completes an operations, it passes the result to the next segment in the pipeline and fetches the next operations from the preceding segment.
  • 21. Idea of pipelining in computer The processor execute the program by fetching and executing instructions. One after the other. Let Fi and Ei refer to the fetch and execute steps for instruction Ii
  • 22. Use the Idea of Pipelining in a Computer
  • 23. Advantages/Disadvantage s Advantages: More efficient use of processor Quicker time of execution of large number of instructions
  • 24. Arithmetic Pipeline Pipeline arithmetic units are usually found in very high speed computers. They are used to implement floating point operations. We will now discuss the pipeline unit for the floating point addition and subtraction.
  • 25. Arithmetic Pipeline The inputs to floating point adder pipeline are two normalized floating point numbers. A and B are mantissas and a and b are the exponents. The floating point addition and subtraction can be performed in four segments.
  • 26. Arithmetic Pipeline The sub-operation performed in each segments are: Compare the exponents Align the mantissas Add or subtract the mantissas Normalize the result
  • 27. Compare Exponent: The exponent are compared by subtracting them to determine their difference. Align the mantissas: The exponent difference determines how many times the mantissas associated with smaller exponent must be shifted to the right.
  • 28. Normalize the result Overflow: Shifted right and exponent increments by one. Underflow: Shifted to left and number must be subtracted from exponent.
  • 31. Instruction Pipeline Pipeline processing can occur not only in the data stream but in the instruction stream as well. An instruction pipeline reads consecutive instruction from memory while previous instruction are being executed in other segments. This caused the instruction fetch and execute segments to overlap and perform simultaneous operation.
  • 33. Instruction Pipeline Instruction execution process lends itself naturally to pipelining overlap the subtasks of instruction fetch, decode and execute Instruction pipeline has six operations, Fetch instruction (FI) Decode instruction (DI) Calculate operands (CO) Fetch operands (FO) Execute instructions (EI) Write result (WR) Overlap these operations
  • 34. Instructions Fetch The IF stage is responsible for obtaining the requested instruction from memory. The instruction and the program counter are stored in the register as temporary storage. Decode Instruction The DI stage is responsible for decoding the instruction and sending out the various control lines to the other parts of the processor.
  • 35. Calculate Operands The CO stage is where any calculations are performed. The main component in this stage is the ALU. The ALU is made up of arithmetic, logic and capabilities. Fetch Operands and Execute Instruction The FO and EI stages are responsible for storing and loading values to and from memory. They also responsible for input and output from the processor respectively.
  • 36. Write Operands The WO stage is responsible for writing the result of a calculation, memory access or input into the register file.
  • 37. Timing Diagram for Instruction Pipeline Operation