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Pragmatic integration of an sram row cache in heterogeneous 3 d dram architecture using tsv

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Ecway Technologies
Ecway Technologies

An SRAM row cache can be integrated into a heterogeneous 3D-DRAM architecture using through-silicon vias to address issues with scaling DRAM cells and improve energy efficiency. The proposed approach stacks DRAM dies vertically and integrates an SRAM row cache. Simulation results show this approach improves performance by 30% and reduces dynamic energy by 31% for memory-intensive applications compared to simple stacking alone.

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PRAGMATIC INTEGRATION OF AN SRAM ROW CACHE IN HETEROGENEOUS 3-D DRAM ARCHITECTURE USING TSV ABSTRACT: As scaling DRAM cells becomes more challenging and energy-efficient DRAM chips are in high demand, the DRAM industry has started to undertake an alternative approach to address these looming issues-that is, to vertically stack DRAM dies with through-silicon-vias (TSVs) using 3-D-IC technology. Furthermore, this emerging integration technology also makes heterogeneous die stacking in one DRAM package possible. Such a heterogeneous DRAM chip provides a unique, promising opportunity for computer architects to contemplate a new memory hierarchy for future system design. In this paper, we study how to design such a heterogeneous DRAM chip for improving both performance and energy efficiency. In particular, we found that, if we want to design an SRAM row cache in a DRAM chip, simple stacking alone cannot address the majority of traditional SRAM row cache design issues. In this paper, to address these issues, we propose a novel floor plan and several architectural techniques that fully exploit the benefits of 3-D stacking technology. Our multi-core simulation results with memory-intensive applications suggest that, by tightly integrating a small row cache with its corresponding DRAM array, we can improve performance by 30% while saving dynamic energy by 31%.

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Pragmatic integration of an sram row cache in heterogeneous 3 d dram architecture using tsv

  • 1. PRAGMATIC INTEGRATION OF AN SRAM ROW CACHE IN HETEROGENEOUS 3-D DRAM ARCHITECTURE USING TSV ABSTRACT: As scaling DRAM cells becomes more challenging and energy-efficient DRAM chips are in high demand, the DRAM industry has started to undertake an alternative approach to address these looming issues-that is, to vertically stack DRAM dies with through-silicon-vias (TSVs) using 3-D-IC technology. Furthermore, this emerging integration technology also makes heterogeneous die stacking in one DRAM package possible. Such a heterogeneous DRAM chip provides a unique, promising opportunity for computer architects to contemplate a new memory hierarchy for future system design. In this paper, we study how to design such a heterogeneous DRAM chip for improving both performance and energy efficiency. In particular, we found that, if we want to design an SRAM row cache in a DRAM chip, simple stacking alone cannot address the majority of traditional SRAM row cache design issues. In this paper, to address these issues, we propose a novel floor plan and several architectural techniques that fully exploit the benefits of 3-D stacking technology. Our multi-core simulation results with memory-intensive applications suggest that, by tightly integrating a small row cache with its corresponding DRAM array, we can improve performance by 30% while saving dynamic energy by 31%.