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 Basic fabrication steps.
 Transistor structures.
 Basic transistor behavior.
 Latch up.

presentation_fabrication_1483089689_242068.pptx

 IC built on silicon substrate:
◦ some structures diffused into substrate;
◦ other structures built on top of substrate.
 Substrate regions are doped with n-type and
p-type impurities. (n+ = heavily doped)
 Wires made of polycrystalline silicon (poly),
multiple layers of aluminum (metal).
 Silicon dioxide (SiO2) is insulator.

substrate
n+ n+
p+
substrate
metal1
poly
SiO2
metal2
metal3
transistor via

Mask patterns are put on wafer using photo-
sensitive material:

First place tubs to provide properly-doped
substrate for n-type, p-type transistors:
p-tub p-tub
substrate

Pattern polysilicon before diffusion regions:
p-tub p-tub
poly poly
gate oxide

Add diffusions, performing self-masking:
p-tub p-tub
poly poly
n+
n+ p+ p+

Start adding metal layers:
p-tub p-tub
poly poly
n+
n+ p+ p+
metal 1 metal 1
vias

poly
silicide
source/drain
gate oxide

 Linear region (Vds < Vgs - Vt):
◦ Id = k’ (W/L)(Vgs - Vt)(Vds - 0.5 Vds
2)
 Saturation region (Vds >= Vgs - Vt):
◦ Id = 0.5k’ (W/L)(Vgs - Vt) 2

Typical values:
 n-type:
◦ kn’ = 170 A/V2
◦ Vtn = 0.5 V
 p-type:
◦ kp’ = 30 A/V2
◦ Vtp = -0.5 V

Use 180 nm parameters. Let W/L = 3/2.
Measure at boundary between linear and
saturation regions.
 Vgs = 0.7V:
Id = 0.5k’(W/L)(Vgs-Vt)2= 5.3 A
 Vgs = 1.2V:
Id = 62 A

 Gate to substrate, also gate to source/drain.
 Source/drain capacitance, resistance.

 Gate capacitance Cg. Determined by active
area.
 Source/drain overlap capacitances Cgs, Cgd.
Determined by source/gate and drain/gate
overlaps. Independent of transistor L.
◦ Cgs = Col W
 Gate/bulk overlap capacitance.

 CMOS ICs have parastic silicon-controlled
rectifiers (SCRs).
 When powered up, SCRs can turn on, creating
low-resistance path from power to ground.
Current can destroy chip.
 Early CMOS problem. Can be solved with
proper circuit/layout structures.

Use tub ties to connect tub to power rail. Use
enough to create low-voltage connection.

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presentation_fabrication_1483089689_242068.pptx

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