Refresh your memory 1
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The document describes a VHDL code for a 5-input AND gate with 8 errors. It lists the port signals X1 and X2 as inputs and Y as the output. The errors include: 1) Not using a package to define std_logic operations, 2) Starting the entity name with a number, 3) Using the wrong data type for the port signals, 4) Incorrect range specified for the port signals, 5) Missing semicolon, 6) Specifying the architecture for the wrong entity, 7) Missing reserved word 'begin', and 8) Wrong architecture name specified.
![Refresh Your Memory [Solution]
5
X1
Y
• Click to edit Master text styles X2 5
AND_GATE
5
– Second level
library IEEE;
• Third level
USE ieee.std_logic_1164.all; -- 1 Use Package to define
operations on std_logic data type
– Fourth
Entity AND_GATE is level -- 2 Don’t Start with number
Port (
» Fifth level
X1 : in std_logic_vector(4 downto 0 ); -- 3 wrong data type
X2 : in std_logic_vector(4 downto 0 ); -- 4 4 downto 0
Y : out std_logic_vector(4 downto 0 ); -- 5 No ;
);
END AND_GATE;
Architecture Behave of AND_GATE IS -- 6 architecture of above entity
Begin --7 Reserved word
Y <= X1 AND X2 ;
END behave ; -- 8 architecture name
Session Two 3](https://image.slidesharecdn.com/refreshyourmemory1-120712155743-phpapp01/85/Refresh-your-memory-1-3-320.jpg)
Refresh your memory 1
- 1. • Click to edit Master text styles – Second level • Third level – Fourthg i t a l D e s i g n u s i n g V H D L D i level Session Two » Fifth level Refresh Your Memory Introduced by Name : Group : Cairo-Egypt Session Zero Version 03 – June 2012 1
- 2. Refresh Your Memory 5 X1 Y • Click to this code Find the 8 errors inedit Master text styles X2 5 AND_GATE 5 – Second level library IEEE; • Third level Entity 5_AND_GATE is Port ( – Fourth level X1 : in std_logic(5 downto 0 ); » Fifth level X2 : in std_logic(5 downto 0 ); Y : out std_logic(5 downto 0 ); ); END 5_and_gate; Architecture Behave of AND_GATE_5 IS Y <= X1 AND X2 ; END 5_AND_GATE; Session Two 2
- 3. Refresh Your Memory [Solution] 5 X1 Y • Click to edit Master text styles X2 5 AND_GATE 5 – Second level library IEEE; • Third level USE ieee.std_logic_1164.all; -- 1 Use Package to define operations on std_logic data type – Fourth Entity AND_GATE is level -- 2 Don’t Start with number Port ( » Fifth level X1 : in std_logic_vector(4 downto 0 ); -- 3 wrong data type X2 : in std_logic_vector(4 downto 0 ); -- 4 4 downto 0 Y : out std_logic_vector(4 downto 0 ); -- 5 No ; ); END AND_GATE; Architecture Behave of AND_GATE IS -- 6 architecture of above entity Begin --7 Reserved word Y <= X1 AND X2 ; END behave ; -- 8 architecture name Session Two 3