ºÝºÝߣ

ºÝºÝߣShare a Scribd company logo

Sai Dheeraj_Resume

•
•
Sai Dheeraj Polagani
Sai Dheeraj Polagani

This document contains Sai Dheeraj Polagani's resume. It includes his contact information, objective, education history, industrial experience at Intel as a physical design engineer and layout engineer, previous experience at Wipro Technologies as an ASIC physical design and verification engineer, technical skills, projects completed and academic projects during his Master's program. His experience includes full-chip static timing analysis, noise analysis, cross-talk analysis, place and route, timing closure, and physical verification. He has a Master's in Electrical Engineering from San Jose State University and a Bachelors in Information and Communication Technology from DA-IICT, India.

1 of 2
1535 N Scottsdale Rd, #2165 Tempe, AZ – 85281. SAI DHEERAJ POLAGANI saidheeraj@ymail.com Phone: (469)-999-2376 OBJECTIVE EDUCATION INDUSTRIAL EXPERIENCE Looking for Full-time Opportunities in ASIC Static Timing Analysis and SOC Physical Design. Industrial Experience: 4 Years Work Authorization: STEM OPT on F1 Student VISA San Jose State University, San Jose, California, U.S. Aug. ‘13 – May ‘15 Master of Science, Electrical Engineering GPA: 3.77/4 Coursework: Digital System Design and Synthesis, Advanced Computer Architecture. Dhirubhai Ambani Institute of Information and Communication Technology (DA-IICT) Gandhinagar, Gujarat, India. July, 2007 – May, 2011 B.Tech., Information and Communication Technology CGPA: 7.09/10.0 Coursework: Computer Organization, Digital System Architecture, Embedded Hardware Design Intel Corporation, Chandler, Arizona, USA. Physical Design Engineer (PDG) June 2015 - Present Full-Chip Static Timing Analysis.  Guard-Banding methodology for best/worst case timing analysis.  Parametric On-Chip Variation Methodology  Simultaneous Multi Voltage Timing Analysis utilizing Unified Power Format (UPF).  Cross-Talk and Noise Analysis.  Generating constraints, maintaining scripts/methodologies to run STA and analyze the results.  Working with Physical Design Engineers to determine how failing paths should be addressed/fixed Intel Corporation, Bangalore, India. Layout Engineer (Contract Worker) May 2013 – July 2013 Section Layout Integration activity for Intel's next generation multi-core processor for servers. Semiconductors and System Solutions, Wipro Technologies Bangalore, Karnataka, India. ASIC Physical Design Engineer June, 2011 – December 2012  Complete Semi-Custom ASIC Physical Design Flow involving Synthesis, Design Planning, IO Planning, Floor-Planning, Power Planning, Place and Route, Clock Tree Synthesis, Timing Analysis and Closure.  Knowledge of LEC, Electro-Migration, IR-Drop, Cross talks, Signal Integrity issues, SSO, ESD and IC Packaging. ASIC Physical Verification Engineer January, 2013 – April, 2013  Physical Verification at 14nm node involving DRC (Design rule check), LVS (Layout versus Schematic), ERC (Electrical Rule Check), XOR (Exclusive OR), and Antenna Checks.  Exposure to DFM (Design for Manufacturability) techniques and Double Patterning Technology. Double Patterning Technology - Impact on VLSI CAD, Cerebration '13, Technical Paper Symposium at Wipro Technologies, Bangalore, India. April 2013 Programming Languages: C, C++, Verilog (HDL), PERL (Scripting), TCL VLSI CAD: Synopsys Primetime, Synopsys IC Compiler, Synopsys Design Compiler, ModelSim, Synopsys VCS, Cadence EDI, Synopsys Astro, Synopsys IC Validator, Matlab, Xilinx Platform Studio, Xilinx ISE. Full Chip Timing Closure for Cable Modem IC June 2015 – May 2016  Noise Analysis and Scan Corner Closure for the Industry’s first DOCSIS 3.0 modem at 14nm. ARM Cortex A9 Hardening Using Reference Methodology from Cadence March 2012 – July 2012  CPF driven low power - high performance design flow to achieve the highest possible frequency exploring multiple options from RTL Synthesis to Detail Routing. Design Compiler Topographical Synthesis Activity August 2012  Completed the feasibility analysis for migrating the RTL Code from 120MHz to 180MHz for different Client Libraries exploring the Synopsys IC Design Compiler Topographical Methodology. Block Level Place and Route for Mobile Communication IC October 2012 – December 2012  Place and Route for a block approximately 2500x2200um with 4M Gates using Synopsys ICC. TECHNICAL PRESENT’ION SKILLS PROJECTS
ACEDEMIC PROJECTS Netlist to Post-Route Implementation of LEON-3, Quad-Core Processor for Synopsys 90nm Technology Generic Library. (Corporate Learning Project) November 2011 – February 2012 Performance Evaluation of Matrix Multiplication on two RTL level designs of Cache Controllers, designed based on Intel Nehalem and AMD Opteron quad-core Cache architectures. Master’s Program Project. August 2014 to May 2015 Hardware Design (Verilog) and Synthesis (Design Compiler) of Correlator for Direct Sequence PSK Spread Spectrum Engine. October 2014 to December 2014  The module is designed to find the frequency and phase of a direct sequence PSK spread spectrum (SS) signal mixed with several other SS signals below the noise floor. The design block will correlate the ADC samples to a pseudo random number (PRN) generator. The generator provides a phase reversal of a sin wave as modulation. Token Passing Ring Bus Design for a System On Chip (SOC) October 2014 to December 2014  Hardware Design: The project was to connect 6 devices (Different SOC Modules viz. RTC, VIC, SSP) together on a token passing ring bus. The project has two such rings, with each of them utilized for different operations. Image Warping with Affine Transformations using Homographic Matrix to Scale/Shrink/Rotate an image. October 2014 to November 2014  Hardware Design: Image warping is the process of digitally manipulating an image such that any shapes portrayed in the image have been significantly distorted. Warping may be used for correcting image distortion. Image Warping revolves around geometric spatial transformations on these images to change the position of the pixels so that the effect would be a morphed or a warped image. Feature Extraction (Corner Points) using Tomasi and Kanade’s Algorithm for Image Processing Applications. October 2014 to November 2014  Hardware Design: In pattern recognition and in image processing, feature extraction is a special form of dimensionality reduction. The project aims to design, synthesize, and simulate the working of the feature points extraction algorithm based on Tomasi and Kanade’s Algorithm for finding Corner Points, which is essential in various image processing applications. This algorithm employs Prewitt Operator, to use it with the edge-detection algorithm. Full-Search Block Matching Algorithm for Motion Estimation Using SAD (Sum of Absolute Differences) September 2014 to October 2014  The project aims to design, synthesize, and simulate the working of the full-search block matching algorithm which is essential in various image and video processing applications including video stabilization, video compression, and stereo vision. The design was later pipe-lined into three- stages with parallel SAD units to increase performance. RGB to YCrCb Color Space Converter (CSC) August 2014 to September 2014  A CSC converts signals from one color space to another color space. The project involved developing an nxn multiply-and-accumulate (MAC) circuit using Altera MegaWizard. The multiplier was designed to perform Fixed Point Multiplication, where the input operands to the MAC engine would be in 2C fractional format. The MAC engine also had a rounding and saturation logic built in. Decimation (2) Poly-Phase FIR Filter (Multi-Rate Filter) December 2014  Hardware Design: The Decimation Filter is actually of order of 2; which means Y (n) 2! = Y (2n). Since, M=2, the decimation factor; the polyphase filter has two sub-filters and where the input data can be computed paralleling across both the filters and then added for the final result. Each output Y (n) is generated in one clock cycle employing two sub-filters parallel. Single Cycle and 5-Stage Pipelined MIPS32 Processor Design and Synthesis, with 4KB Separate Data and Instruction Cache including Prefetching Support. March 2014 to May 2014  Design of MIPS32 5-Stage Pipelined Processor (with Hazard Detection and Data Forwarding), with 4KB 2-Way Associative Instruction Cache and write-through, no-write allocate Data Cache. Pipelined Cyclic Redundancy Checker (CRC-9) November 2014  Hardware Design: A Cyclic Redundancy Check (CRC) is the remainder, or residue, of binary division of a potentially long message, by a CRC polynomial. This project presents implementation of pipelined Cyclic Redundancy Check (CRC-9) based upon DSP algorithms of pipelining. The architecture is pipelined to reduce the iteration bound by using novel look-ahead techniques. Hamming Code (12,8) Encoder and Decoder Design and Synthesis March 2014 to April 2014  Design and Synthesis of Hamming Function (12, 8) to encode a byte of data using 4-parity bits and decode data, including one-bit error correction.

More Related Content

Sai Dheeraj_Resume

  • 1. 1535 N Scottsdale Rd, #2165 Tempe, AZ – 85281. SAI DHEERAJ POLAGANI saidheeraj@ymail.com Phone: (469)-999-2376 OBJECTIVE EDUCATION INDUSTRIAL EXPERIENCE Looking for Full-time Opportunities in ASIC Static Timing Analysis and SOC Physical Design. Industrial Experience: 4 Years Work Authorization: STEM OPT on F1 Student VISA San Jose State University, San Jose, California, U.S. Aug. ‘13 – May ‘15 Master of Science, Electrical Engineering GPA: 3.77/4 Coursework: Digital System Design and Synthesis, Advanced Computer Architecture. Dhirubhai Ambani Institute of Information and Communication Technology (DA-IICT) Gandhinagar, Gujarat, India. July, 2007 – May, 2011 B.Tech., Information and Communication Technology CGPA: 7.09/10.0 Coursework: Computer Organization, Digital System Architecture, Embedded Hardware Design Intel Corporation, Chandler, Arizona, USA. Physical Design Engineer (PDG) June 2015 - Present Full-Chip Static Timing Analysis. ï‚· Guard-Banding methodology for best/worst case timing analysis. ï‚· Parametric On-Chip Variation Methodology ï‚· Simultaneous Multi Voltage Timing Analysis utilizing Unified Power Format (UPF). ï‚· Cross-Talk and Noise Analysis. ï‚· Generating constraints, maintaining scripts/methodologies to run STA and analyze the results. ï‚· Working with Physical Design Engineers to determine how failing paths should be addressed/fixed Intel Corporation, Bangalore, India. Layout Engineer (Contract Worker) May 2013 – July 2013 Section Layout Integration activity for Intel's next generation multi-core processor for servers. Semiconductors and System Solutions, Wipro Technologies Bangalore, Karnataka, India. ASIC Physical Design Engineer June, 2011 – December 2012 ï‚· Complete Semi-Custom ASIC Physical Design Flow involving Synthesis, Design Planning, IO Planning, Floor-Planning, Power Planning, Place and Route, Clock Tree Synthesis, Timing Analysis and Closure. ï‚· Knowledge of LEC, Electro-Migration, IR-Drop, Cross talks, Signal Integrity issues, SSO, ESD and IC Packaging. ASIC Physical Verification Engineer January, 2013 – April, 2013 ï‚· Physical Verification at 14nm node involving DRC (Design rule check), LVS (Layout versus Schematic), ERC (Electrical Rule Check), XOR (Exclusive OR), and Antenna Checks. ï‚· Exposure to DFM (Design for Manufacturability) techniques and Double Patterning Technology. Double Patterning Technology - Impact on VLSI CAD, Cerebration '13, Technical Paper Symposium at Wipro Technologies, Bangalore, India. April 2013 Programming Languages: C, C++, Verilog (HDL), PERL (Scripting), TCL VLSI CAD: Synopsys Primetime, Synopsys IC Compiler, Synopsys Design Compiler, ModelSim, Synopsys VCS, Cadence EDI, Synopsys Astro, Synopsys IC Validator, Matlab, Xilinx Platform Studio, Xilinx ISE. Full Chip Timing Closure for Cable Modem IC June 2015 – May 2016 ï‚· Noise Analysis and Scan Corner Closure for the Industry’s first DOCSIS 3.0 modem at 14nm. ARM Cortex A9 Hardening Using Reference Methodology from Cadence March 2012 – July 2012 ï‚· CPF driven low power - high performance design flow to achieve the highest possible frequency exploring multiple options from RTL Synthesis to Detail Routing. Design Compiler Topographical Synthesis Activity August 2012 ï‚· Completed the feasibility analysis for migrating the RTL Code from 120MHz to 180MHz for different Client Libraries exploring the Synopsys IC Design Compiler Topographical Methodology. Block Level Place and Route for Mobile Communication IC October 2012 – December 2012 ï‚· Place and Route for a block approximately 2500x2200um with 4M Gates using Synopsys ICC. TECHNICAL PRESENT’ION SKILLS PROJECTS
  • 2. ACEDEMIC PROJECTS Netlist to Post-Route Implementation of LEON-3, Quad-Core Processor for Synopsys 90nm Technology Generic Library. (Corporate Learning Project) November 2011 – February 2012 Performance Evaluation of Matrix Multiplication on two RTL level designs of Cache Controllers, designed based on Intel Nehalem and AMD Opteron quad-core Cache architectures. Master’s Program Project. August 2014 to May 2015 Hardware Design (Verilog) and Synthesis (Design Compiler) of Correlator for Direct Sequence PSK Spread Spectrum Engine. October 2014 to December 2014 ï‚· The module is designed to find the frequency and phase of a direct sequence PSK spread spectrum (SS) signal mixed with several other SS signals below the noise floor. The design block will correlate the ADC samples to a pseudo random number (PRN) generator. The generator provides a phase reversal of a sin wave as modulation. Token Passing Ring Bus Design for a System On Chip (SOC) October 2014 to December 2014 ï‚· Hardware Design: The project was to connect 6 devices (Different SOC Modules viz. RTC, VIC, SSP) together on a token passing ring bus. The project has two such rings, with each of them utilized for different operations. Image Warping with Affine Transformations using Homographic Matrix to Scale/Shrink/Rotate an image. October 2014 to November 2014 ï‚· Hardware Design: Image warping is the process of digitally manipulating an image such that any shapes portrayed in the image have been significantly distorted. Warping may be used for correcting image distortion. Image Warping revolves around geometric spatial transformations on these images to change the position of the pixels so that the effect would be a morphed or a warped image. Feature Extraction (Corner Points) using Tomasi and Kanade’s Algorithm for Image Processing Applications. October 2014 to November 2014 ï‚· Hardware Design: In pattern recognition and in image processing, feature extraction is a special form of dimensionality reduction. The project aims to design, synthesize, and simulate the working of the feature points extraction algorithm based on Tomasi and Kanade’s Algorithm for finding Corner Points, which is essential in various image processing applications. This algorithm employs Prewitt Operator, to use it with the edge-detection algorithm. Full-Search Block Matching Algorithm for Motion Estimation Using SAD (Sum of Absolute Differences) September 2014 to October 2014 ï‚· The project aims to design, synthesize, and simulate the working of the full-search block matching algorithm which is essential in various image and video processing applications including video stabilization, video compression, and stereo vision. The design was later pipe-lined into three- stages with parallel SAD units to increase performance. RGB to YCrCb Color Space Converter (CSC) August 2014 to September 2014 ï‚· A CSC converts signals from one color space to another color space. The project involved developing an nxn multiply-and-accumulate (MAC) circuit using Altera MegaWizard. The multiplier was designed to perform Fixed Point Multiplication, where the input operands to the MAC engine would be in 2C fractional format. The MAC engine also had a rounding and saturation logic built in. Decimation (2) Poly-Phase FIR Filter (Multi-Rate Filter) December 2014 ï‚· Hardware Design: The Decimation Filter is actually of order of 2; which means Y (n) 2! = Y (2n). Since, M=2, the decimation factor; the polyphase filter has two sub-filters and where the input data can be computed paralleling across both the filters and then added for the final result. Each output Y (n) is generated in one clock cycle employing two sub-filters parallel. Single Cycle and 5-Stage Pipelined MIPS32 Processor Design and Synthesis, with 4KB Separate Data and Instruction Cache including Prefetching Support. March 2014 to May 2014 ï‚· Design of MIPS32 5-Stage Pipelined Processor (with Hazard Detection and Data Forwarding), with 4KB 2-Way Associative Instruction Cache and write-through, no-write allocate Data Cache. Pipelined Cyclic Redundancy Checker (CRC-9) November 2014 ï‚· Hardware Design: A Cyclic Redundancy Check (CRC) is the remainder, or residue, of binary division of a potentially long message, by a CRC polynomial. This project presents implementation of pipelined Cyclic Redundancy Check (CRC-9) based upon DSP algorithms of pipelining. The architecture is pipelined to reduce the iteration bound by using novel look-ahead techniques. Hamming Code (12,8) Encoder and Decoder Design and Synthesis March 2014 to April 2014 ï‚· Design and Synthesis of Hamming Function (12, 8) to encode a byte of data using 4-parity bits and decode data, including one-bit error correction.