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Satish Sambangi
Satish Sambangi

Sambangi Satishkumar is pursuing an M.Tech in VLSI from Vellore Institute of Technology with a CGPA of 8.67. He has a B.Tech in ECE from Lovely Professional University with a percentage of 8.45. His technical skills include EDA tools like Mentor Graphics Modelsim, Quartus II, Synopsys DC and ICC, and Cadence Virtuoso. He has experience with hardware description languages like Verilog and software skills in C, C++ and Perl. His areas of technical expertise are in semiconductor physics, digital IC design, FPGA-based system design and low power IC design. He has worked on projects implementing a low power ASIC

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CURRICULUM VITAE Sambangi Satishkumar 3-018, Pakki (Post) Bobbili(Mandal) Vizianagaram (Dist) Andhra Pradesh (State) Pin code - 535558 Email id:satishsambangi3@gmail.com Phone no: +91-9585581281 CAREER OBJECTIVE: To secure a challenging position in a VLSI design field where I can effectively contribute my knowledge as a Engineering professional possessing competent technical skills with passion. EDUCATIONAL QUALIFICATIONS: Degree / Institution/ Year CGPAPercentage Certificate Board M.Tech VLSI Vellore Institute of Technology Pursuing 8.67 B.Tech ECE Lovely Professional University 2014 8.45 Phagwara
HSC Sri Chaitanya Jr.college 2010 92.10% Visikhapatnam SSC APRS High School 2008 90.01% Bobbili TECHNICAL SKILLS: EDA Tools : Mentor Graphics Modelsim-Altera, Quartus – II, Synopsys DC, Synopsys ICC, Cadence Virtuoso, Cadence RC. Hardware Description Languages: Verilog HDL Software Skills : C,C++, Perl Platforms : Linux, Windows. Hardware Expertise : Altera FPGA DE1 Board(Digital System Design) TECHNICAL EXPERTISE: Semiconductor Physics, Digital IC Design, FPGA Based System Design, Low Power IC Design, CMOS VLSI Design, ASIC Design, Scripting and Verification Languages, VLSI Testing and Testability, Analog IC design, Mixed Signal IC design PROJECTS UNDER TAKEN: Low Power ASIC Implementation of Hybrid VLSI DPWM Architecture (Jan 2016– May 2016 ): In this Project a modified Hybrid DPWM(Digital Pulse Width Modulator) architecture employing XNOR-delay line to achieve high resolution and variable duty cycle with low power consumption. In this design, existing DPWM architecture with adder delay line is modified to a DPWM architecture with adders replaced by XNOR-gates. The multi VDD(UPF_flow) low power technique at system level applied to the proposed architecture consists of two voltage levels 0.95 V(for Critical path) and 0.7 V, which are used to provide different voltages to different blocks in the design and targeted for 32nm library with Synopsys DC.
Implementation of Inexact floating point Adder Architecture (Jan 2016– May 2016 ): In this project a Low power Inexact floating point adder is Implemented with ASIC flow and reported various aspects after synthesis with targeted for 90nm library with Synopsys DC. This adder takes less time to compute the mantissa addition because inexact adder (Lower-part-OR) is used for LSB bits .This involves in decimal to binary conversion ,exponent comparison, mantissa shifting ,mantissa addition ,normalization. This architecture is useful for image processing applications where low accuracy is needed. Implementation of CMOS Transconductance Multipliers(Jul 2015– Dec 2015) : Multiplication is a non linear operation in analog signal processing. The Multiplier is implemented using gpdk90 nm technology in Cadence Spectre Environment and studied through simulation. Realized multiplication operation by basic Gilbert cell and implemented by propriety of voltage to current conversion. All MOSFETS are operated in saturation region to get undistorted output and constant gain. Multiplication Circuit is observed by the following properties linearity range, total Harmonic Distortion and modulation property. Design and effective digital testing of Voltage Control Oscillators(Jul 2015– Dec 2015): In this project the Voltage Control Oscillator is designed with Cadence tool and studied through simulation,which covers maximum fault coverage. By observing the delay between different stages of simple VCO circuit, reconfigurable VCO circuit and also observe the delay between elements by changing the supply voltage and transistor sizing . The frequency generation is mainly depends on supply voltage , no of amplifier stages and transistor sizing ratio. For generating clock frequencies in Mega Hertz we have to use three stage ring oscillator, in Giga Hertz we have to use five stage ring oscillator. Papers Published: 1.Oral Presentation for Set Conference 12 Low Power ASIC Implementation of Hybrid VLSI DPWM Architecture 2. Published a paper entitled Fused Floating Point Adder and Subtract Unit in IEEE Sponsored Online International Conference on Green Engineering & Technologies. WORKSHOPS / CERTIFICATIONS/ SEMINARS:
Matlab Workshop in Learning of Image Processing in November 2013 held at Lovely Professional University Analog VLSI Design Workshop in Learning of Analog concepts in Feburary 2016 held at C-DAC Bangalore Device to GDSII for IC Design in learning of learning of VLSI Design Flow in Feburary 2016 held at Vellore Institute of Technology. EXTRA CURRICULAR ACTIVITIES: Participated in : One India in Lovely Professional University 2012 One World in Lovely Professional University 2012 International Youth Fellowship Camp Delhi 2012 Induction Ceremony Lovely Professional University 2012 AWARDS AND HONOURS: VITMEE All India 4th Rank -2015 –VIT University Bronze Medal - Annual Athletic Meet 4*400 Relay, 2013 NSS Group Leader 2011-13 NCC cadet 2007-08 LANGUAGES KNOWN: English, Hindi &Telugu HOBBIES: Reading Newspaper, Athletics ,Yoga
PERSONAL DETAILS: Date of Birth : 10–07–1993 Gender : Male DATE: 19-05-2016 PLACE: vellore S.SATISHKUMAR
PERSONAL DETAILS: Date of Birth : 10–07–1993 Gender : Male DATE: 19-05-2016 PLACE: vellore S.SATISHKUMAR

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satish real

  • 1. CURRICULUM VITAE Sambangi Satishkumar 3-018, Pakki (Post) Bobbili(Mandal) Vizianagaram (Dist) Andhra Pradesh (State) Pin code - 535558 Email id:satishsambangi3@gmail.com Phone no: +91-9585581281 CAREER OBJECTIVE: To secure a challenging position in a VLSI design field where I can effectively contribute my knowledge as a Engineering professional possessing competent technical skills with passion. EDUCATIONAL QUALIFICATIONS: Degree / Institution/ Year CGPAPercentage Certificate Board M.Tech VLSI Vellore Institute of Technology Pursuing 8.67 B.Tech ECE Lovely Professional University 2014 8.45 Phagwara
  • 2. HSC Sri Chaitanya Jr.college 2010 92.10% Visikhapatnam SSC APRS High School 2008 90.01% Bobbili TECHNICAL SKILLS: EDA Tools : Mentor Graphics Modelsim-Altera, Quartus – II, Synopsys DC, Synopsys ICC, Cadence Virtuoso, Cadence RC. Hardware Description Languages: Verilog HDL Software Skills : C,C++, Perl Platforms : Linux, Windows. Hardware Expertise : Altera FPGA DE1 Board(Digital System Design) TECHNICAL EXPERTISE: Semiconductor Physics, Digital IC Design, FPGA Based System Design, Low Power IC Design, CMOS VLSI Design, ASIC Design, Scripting and Verification Languages, VLSI Testing and Testability, Analog IC design, Mixed Signal IC design PROJECTS UNDER TAKEN: Low Power ASIC Implementation of Hybrid VLSI DPWM Architecture (Jan 2016– May 2016 ): In this Project a modified Hybrid DPWM(Digital Pulse Width Modulator) architecture employing XNOR-delay line to achieve high resolution and variable duty cycle with low power consumption. In this design, existing DPWM architecture with adder delay line is modified to a DPWM architecture with adders replaced by XNOR-gates. The multi VDD(UPF_flow) low power technique at system level applied to the proposed architecture consists of two voltage levels 0.95 V(for Critical path) and 0.7 V, which are used to provide different voltages to different blocks in the design and targeted for 32nm library with Synopsys DC.
  • 3. Implementation of Inexact floating point Adder Architecture (Jan 2016– May 2016 ): In this project a Low power Inexact floating point adder is Implemented with ASIC flow and reported various aspects after synthesis with targeted for 90nm library with Synopsys DC. This adder takes less time to compute the mantissa addition because inexact adder (Lower-part-OR) is used for LSB bits .This involves in decimal to binary conversion ,exponent comparison, mantissa shifting ,mantissa addition ,normalization. This architecture is useful for image processing applications where low accuracy is needed. Implementation of CMOS Transconductance Multipliers(Jul 2015– Dec 2015) : Multiplication is a non linear operation in analog signal processing. The Multiplier is implemented using gpdk90 nm technology in Cadence Spectre Environment and studied through simulation. Realized multiplication operation by basic Gilbert cell and implemented by propriety of voltage to current conversion. All MOSFETS are operated in saturation region to get undistorted output and constant gain. Multiplication Circuit is observed by the following properties linearity range, total Harmonic Distortion and modulation property. Design and effective digital testing of Voltage Control Oscillators(Jul 2015– Dec 2015): In this project the Voltage Control Oscillator is designed with Cadence tool and studied through simulation,which covers maximum fault coverage. By observing the delay between different stages of simple VCO circuit, reconfigurable VCO circuit and also observe the delay between elements by changing the supply voltage and transistor sizing . The frequency generation is mainly depends on supply voltage , no of amplifier stages and transistor sizing ratio. For generating clock frequencies in Mega Hertz we have to use three stage ring oscillator, in Giga Hertz we have to use five stage ring oscillator. Papers Published: 1.Oral Presentation for Set Conference 12 Low Power ASIC Implementation of Hybrid VLSI DPWM Architecture 2. Published a paper entitled Fused Floating Point Adder and Subtract Unit in IEEE Sponsored Online International Conference on Green Engineering & Technologies. WORKSHOPS / CERTIFICATIONS/ SEMINARS:
  • 4. Matlab Workshop in Learning of Image Processing in November 2013 held at Lovely Professional University Analog VLSI Design Workshop in Learning of Analog concepts in Feburary 2016 held at C-DAC Bangalore Device to GDSII for IC Design in learning of learning of VLSI Design Flow in Feburary 2016 held at Vellore Institute of Technology. EXTRA CURRICULAR ACTIVITIES: Participated in : One India in Lovely Professional University 2012 One World in Lovely Professional University 2012 International Youth Fellowship Camp Delhi 2012 Induction Ceremony Lovely Professional University 2012 AWARDS AND HONOURS: VITMEE All India 4th Rank -2015 –VIT University Bronze Medal - Annual Athletic Meet 4*400 Relay, 2013 NSS Group Leader 2011-13 NCC cadet 2007-08 LANGUAGES KNOWN: English, Hindi &Telugu HOBBIES: Reading Newspaper, Athletics ,Yoga
  • 5. PERSONAL DETAILS: Date of Birth : 10–07–1993 Gender : Male DATE: 19-05-2016 PLACE: vellore S.SATISHKUMAR
  • 6. PERSONAL DETAILS: Date of Birth : 10–07–1993 Gender : Male DATE: 19-05-2016 PLACE: vellore S.SATISHKUMAR
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