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SnUG 1996 - NLD Optimization for ISM - slides

T
Tim55Ehrler

This presentation summarizes the analysis of the most common method of generating a Synopsys non-linear delay (NLD) library from an input-slope model (ISM) description. From this analysis, a much improved method of template/table generation is introduced which minimizes library resource requirements, reduces delay value look-up time, and increases delay derivation accuracy.

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Non-Linear Delay Table Optimization Input Slope Models & Synopsys NLD Table Analysis Analyze previous Synopsys non-linear delay model tables - output load & input ramp range coverage - table value interpolation accuracy Investigate alternate table configurations - smaller, more efficient tables - more accurate sample points - critical sample point distribution 1 of 16 Timothy J. Ehrler VLSI Technology, Inc.
Non-Linear Delay Table Optimization Previous Synopsys Non-Linear Delay Model Tables single stage non-disable timing relationship analyzed 25 x 25 array (output load by input ramp) single template to cover complete library (~300 SS rels) 2 of 16 Timothy J. Ehrler VLSI Technology, Inc.
Non-Linear Delay Table Optimization Fixed Indexed Non-Linear Delay Table Critical Input Ramp Delay Table delay (ns) 25 20 15 10 5 0 9 8 7 6 0 5 0.5 1 4 1.5 3 output load (pf) 2 2.5 2 3 3.5 1 input ramp (ns) 4 3 of 16 Timothy J. Ehrler VLSI Technology, Inc.
Non-Linear Delay Table Optimization Sufficient Rel Table Coverage delay (ns) 2.5 2 1.5 1 Critical Input Ramp 0.5 Base Table 0 0.7 0.6 0.5 0.5 0.4 1 1.5 0.3 2 output load (pf) 2.5 0.2 3 3.5 0.1 input ramp (ns) 4 4.5 0 4 of 16 Timothy J. Ehrler VLSI Technology, Inc.
Non-Linear Delay Table Optimization Base Coverage vs. Fixed Interpolated Values Base Table 2 Fixed Table Interpolation Critical Input Ramp 1.5 1 0.5 0 0.4 0.35 0.3 0.25 0.5 0.2 1 0.15 output load (pf) 1.5 0.1 2 0.05 input ramp (ns) 0 2.5 5 of 16 Timothy J. Ehrler VLSI Technology, Inc.
Non-Linear Delay Table Optimization Base Coverage vs. Fixed Interpolated Errors Fixed Table Interpolation Error at CIR Fixed Table Interpolation Error % error 0 -1 -2 -3 -4 -5 -6 0.4 0.35 -7 0.3 - 7.3 % 0.25 0.5 -8 0.2 1 0.15 output load (pf) 1.5 0.1 2 0.05 input ramp (ns) 0 2.5 6 of 16 Timothy J. Ehrler VLSI Technology, Inc.
Non-Linear Delay Table Optimization Reduced Sufficient Rel Table Coverage Critical Input Ramp Sample Table delay (ns) 2.5 2 1.5 1 0.5 0 0.7 0.6 0.5 0.5 0.4 1 1.5 0.3 2 output load (pf) 2.5 0.2 3 3.5 0.1 input ramp (ns) 4 4.5 0 7 of 16 Timothy J. Ehrler VLSI Technology, Inc.
Non-Linear Delay Table Optimization Base Coverage vs. Reduced Sufficient Interpolated Values Base Table Reduced Sufficient Table Interpolation Critical Input Ramp delay (ns) 2.5 2 1.5 1 0.5 0 0.7 0.6 0.5 0.5 0.4 1 1.5 0.3 output load (pf) 2 2.5 0.2 3 3.5 0.1 input ramp (ns) 4 4.5 0 8 of 16 Timothy J. Ehrler VLSI Technology, Inc.
Non-Linear Delay Table Optimization Base Coverage vs. Reduced Sufficient Interpolated Errors Reduced Sufficient Table Interpolation Error at CIR Reduced Sufficient Table Interpolation Error % error 1 0 -1 -2 -3 -4 -5 - 5.0 % -6 0.2 0.15 0.5 0.1 output load (pf) 1 0.05 input ramp (ns) 0 1.5 9 of 16 Timothy J. Ehrler VLSI Technology, Inc.
Non-Linear Delay Table Optimization Reduced Sufficient vs. Fixed Size Error % error 1 0 -1 -2 -3 -4 -5 -6 -7 -8 Fixed Table Interpolation Error at CIR Fixed Table Interpolation Error 0.7 0.6 Reduced Sufficient Table Interpolation Error at CIR 0.5 0.5 Reduced Sufficient Table Interpolation Error 0.4 1 1.5 0.3 2 output load (pf) 2.5 0.2 3 3.5 0.1 input ramp (ns) 4 4.5 0 10 of 16 Timothy J. Ehrler VLSI Technology, Inc.
Non-Linear Delay Table Optimization Non-Linearly Indexed Table Critical Input Ramp Non-linear Sample Table delay (ns) 3 2.5 2 1.5 1 0.5 0 0.8 0.7 0.6 0.5 0.5 1 0.4 1.5 2 0.3 output load (pf) 2.5 3 0.2 3.5 4 0.1 input ramp (ns) 4.5 5 0 11 of 16 Timothy J. Ehrler VLSI Technology, Inc.
Non-Linear Delay Table Optimization Non-Linearly Indexed Interpolated Values Non-linear Base Table Non-linear Sample Table Interpolation Critical Input Ramp delay (ns) 2.5 2 1.5 1 0.5 0 0.7 0.6 0.5 0.5 0.4 1 1.5 0.3 2 output load (pf) 2.5 0.2 3 3.5 0.1 input ramp (ns) 4 4.5 0 12 of 16 Timothy J. Ehrler VLSI Technology, Inc.
Non-Linear Delay Table Optimization Non-Linearly Indexed Interpolated Errors Non-linear Table Interpolation Error at CIR Non-linear Table Interpolation Error % error 0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 - 3.0 % 0.08 0.07 -3.5 0.06 0.05 0.5 0.55 0.04 0.6 0.03 output load (pf) 0.65 0.7 0.02 0.75 0.8 0.01 input ramp (ns) 0.85 0 13 of 16 Timothy J. Ehrler VLSI Technology, Inc.
Non-Linear Delay Table Optimization Optimized Non-Linearly Indexed vs. Fixed Linearly Indexed Error % error 1 0 -1 -2 -3 -4 -5 -6 -7 -8 Fixed Linearly Indexed Interpolation Error Fixed Linearly Indexed Interpolation Error at CIR 0.7 0.6 Optimized Non-Linearly Indexed Interpolation Error 0.5 0.5 Optimized Non-Linearly Indexed Interpolation Error at CIR 0.4 1 1.5 0.3 2 2.5 0.2 output load (pf) 3 input ramp (ns) 3.5 4 0.1 4.5 14 of 16 Timothy J. Ehrler VLSI Technology, Inc.
Non-Linear Delay Table Optimization Applied Results library containing 538 single-stage non-disable timing rels 5.0 % interpolation error within a 64x64 overlaid matrix Property Previous Current % of Previous minimum size - 3x3 - maximum size - 18x18 - average size 25x25 7.6x7.6 30 % average entries/table 625 57.4 9.2 % total entries 336,250 30,906 9.2 % 15 of 16 Timothy J. Ehrler VLSI Technology, Inc.
Non-Linear Delay Table Optimization Conclusions smaller tables can cover full output load and critical input ramp ranges smaller tables reduce resource usage considerably custom coverage ensures more accurate interpolation non-linear indices assure more accurate critical region coverage 16 of 16 Timothy J. Ehrler VLSI Technology, Inc.

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SnUG 1996 - NLD Optimization for ISM - slides

  • 1. Non-Linear Delay Table Optimization Input Slope Models & Synopsys NLD Table Analysis Analyze previous Synopsys non-linear delay model tables - output load & input ramp range coverage - table value interpolation accuracy Investigate alternate table configurations - smaller, more efficient tables - more accurate sample points - critical sample point distribution 1 of 16 Timothy J. Ehrler VLSI Technology, Inc.
  • 2. Non-Linear Delay Table Optimization Previous Synopsys Non-Linear Delay Model Tables single stage non-disable timing relationship analyzed 25 x 25 array (output load by input ramp) single template to cover complete library (~300 SS rels) 2 of 16 Timothy J. Ehrler VLSI Technology, Inc.
  • 3. Non-Linear Delay Table Optimization Fixed Indexed Non-Linear Delay Table Critical Input Ramp Delay Table delay (ns) 25 20 15 10 5 0 9 8 7 6 0 5 0.5 1 4 1.5 3 output load (pf) 2 2.5 2 3 3.5 1 input ramp (ns) 4 3 of 16 Timothy J. Ehrler VLSI Technology, Inc.
  • 4. Non-Linear Delay Table Optimization Sufficient Rel Table Coverage delay (ns) 2.5 2 1.5 1 Critical Input Ramp 0.5 Base Table 0 0.7 0.6 0.5 0.5 0.4 1 1.5 0.3 2 output load (pf) 2.5 0.2 3 3.5 0.1 input ramp (ns) 4 4.5 0 4 of 16 Timothy J. Ehrler VLSI Technology, Inc.
  • 5. Non-Linear Delay Table Optimization Base Coverage vs. Fixed Interpolated Values Base Table 2 Fixed Table Interpolation Critical Input Ramp 1.5 1 0.5 0 0.4 0.35 0.3 0.25 0.5 0.2 1 0.15 output load (pf) 1.5 0.1 2 0.05 input ramp (ns) 0 2.5 5 of 16 Timothy J. Ehrler VLSI Technology, Inc.
  • 6. Non-Linear Delay Table Optimization Base Coverage vs. Fixed Interpolated Errors Fixed Table Interpolation Error at CIR Fixed Table Interpolation Error % error 0 -1 -2 -3 -4 -5 -6 0.4 0.35 -7 0.3 - 7.3 % 0.25 0.5 -8 0.2 1 0.15 output load (pf) 1.5 0.1 2 0.05 input ramp (ns) 0 2.5 6 of 16 Timothy J. Ehrler VLSI Technology, Inc.
  • 7. Non-Linear Delay Table Optimization Reduced Sufficient Rel Table Coverage Critical Input Ramp Sample Table delay (ns) 2.5 2 1.5 1 0.5 0 0.7 0.6 0.5 0.5 0.4 1 1.5 0.3 2 output load (pf) 2.5 0.2 3 3.5 0.1 input ramp (ns) 4 4.5 0 7 of 16 Timothy J. Ehrler VLSI Technology, Inc.
  • 8. Non-Linear Delay Table Optimization Base Coverage vs. Reduced Sufficient Interpolated Values Base Table Reduced Sufficient Table Interpolation Critical Input Ramp delay (ns) 2.5 2 1.5 1 0.5 0 0.7 0.6 0.5 0.5 0.4 1 1.5 0.3 output load (pf) 2 2.5 0.2 3 3.5 0.1 input ramp (ns) 4 4.5 0 8 of 16 Timothy J. Ehrler VLSI Technology, Inc.
  • 9. Non-Linear Delay Table Optimization Base Coverage vs. Reduced Sufficient Interpolated Errors Reduced Sufficient Table Interpolation Error at CIR Reduced Sufficient Table Interpolation Error % error 1 0 -1 -2 -3 -4 -5 - 5.0 % -6 0.2 0.15 0.5 0.1 output load (pf) 1 0.05 input ramp (ns) 0 1.5 9 of 16 Timothy J. Ehrler VLSI Technology, Inc.
  • 10. Non-Linear Delay Table Optimization Reduced Sufficient vs. Fixed Size Error % error 1 0 -1 -2 -3 -4 -5 -6 -7 -8 Fixed Table Interpolation Error at CIR Fixed Table Interpolation Error 0.7 0.6 Reduced Sufficient Table Interpolation Error at CIR 0.5 0.5 Reduced Sufficient Table Interpolation Error 0.4 1 1.5 0.3 2 output load (pf) 2.5 0.2 3 3.5 0.1 input ramp (ns) 4 4.5 0 10 of 16 Timothy J. Ehrler VLSI Technology, Inc.
  • 11. Non-Linear Delay Table Optimization Non-Linearly Indexed Table Critical Input Ramp Non-linear Sample Table delay (ns) 3 2.5 2 1.5 1 0.5 0 0.8 0.7 0.6 0.5 0.5 1 0.4 1.5 2 0.3 output load (pf) 2.5 3 0.2 3.5 4 0.1 input ramp (ns) 4.5 5 0 11 of 16 Timothy J. Ehrler VLSI Technology, Inc.
  • 12. Non-Linear Delay Table Optimization Non-Linearly Indexed Interpolated Values Non-linear Base Table Non-linear Sample Table Interpolation Critical Input Ramp delay (ns) 2.5 2 1.5 1 0.5 0 0.7 0.6 0.5 0.5 0.4 1 1.5 0.3 2 output load (pf) 2.5 0.2 3 3.5 0.1 input ramp (ns) 4 4.5 0 12 of 16 Timothy J. Ehrler VLSI Technology, Inc.
  • 13. Non-Linear Delay Table Optimization Non-Linearly Indexed Interpolated Errors Non-linear Table Interpolation Error at CIR Non-linear Table Interpolation Error % error 0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 - 3.0 % 0.08 0.07 -3.5 0.06 0.05 0.5 0.55 0.04 0.6 0.03 output load (pf) 0.65 0.7 0.02 0.75 0.8 0.01 input ramp (ns) 0.85 0 13 of 16 Timothy J. Ehrler VLSI Technology, Inc.
  • 14. Non-Linear Delay Table Optimization Optimized Non-Linearly Indexed vs. Fixed Linearly Indexed Error % error 1 0 -1 -2 -3 -4 -5 -6 -7 -8 Fixed Linearly Indexed Interpolation Error Fixed Linearly Indexed Interpolation Error at CIR 0.7 0.6 Optimized Non-Linearly Indexed Interpolation Error 0.5 0.5 Optimized Non-Linearly Indexed Interpolation Error at CIR 0.4 1 1.5 0.3 2 2.5 0.2 output load (pf) 3 input ramp (ns) 3.5 4 0.1 4.5 14 of 16 Timothy J. Ehrler VLSI Technology, Inc.
  • 15. Non-Linear Delay Table Optimization Applied Results library containing 538 single-stage non-disable timing rels 5.0 % interpolation error within a 64x64 overlaid matrix Property Previous Current % of Previous minimum size - 3x3 - maximum size - 18x18 - average size 25x25 7.6x7.6 30 % average entries/table 625 57.4 9.2 % total entries 336,250 30,906 9.2 % 15 of 16 Timothy J. Ehrler VLSI Technology, Inc.
  • 16. Non-Linear Delay Table Optimization Conclusions smaller tables can cover full output load and critical input ramp ranges smaller tables reduce resource usage considerably custom coverage ensures more accurate interpolation non-linear indices assure more accurate critical region coverage 16 of 16 Timothy J. Ehrler VLSI Technology, Inc.
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