![Somesh Mishra
Tessolve Semiconductors
Bhubaneswar Email: somesh.mishra@tessolve.com
Odisha , India – 751013 Mobile: +91-9090965929
_______________________________________________________________________
VLSI Domain Skills
HDL: Verilog
HVL: SystemVerilog
Verification Methodologies: Coverage Driven Verification
Assertion Based Verification - SVA
TB Methodology: UVM
EDA Tool: VCS, Verdi, DVT, Questasim, Modelsim, NCSim and ISE
Domain: ASIC/FPGA Front-end Design and Verification
Knowledge: RTL Coding, Simulation, Code Coverage, Functional Coverage,
Synthesis, SVA
Scripting language: Perl
Experience
Tessolve Semiconductors (Acquired Aims Technology Inc.) Jan 2016 – Current
Maven Silicon VLSI Design and Verification Center, Bangalore June to August 2015
QSocs Technologies, August to Dec 2015
[1]Pcie2Axi and Axi2Pcie traffic: (Client Broadcom )
Description
The axi transactions were converted to pcie transaction with internal addressing logics and
inbound/outbound memory logics. Was given the task of generating axi to pcie traffic and
vice versa and writing checker for few scenarios.
Responsibilities:
 In Axi2pcie path wrote testcase for Axi transfers and checker for pcie ,writing
checker for wrap burst, writing checker for unaligned aligned addressing w.r.t pcie
 Develop testcase to generate axi burst transfer, aligned and unaligned addressing.
 Develop testcase for Wrap data transfer and writing checker for the unaligned
addressing and wrap addressing. Writing Checker for pcie TL packets. Checked fbe,
lbe, payload, address, th, tc etc..
 Ran regression for axi to pcie path and done debugging.
 Implementing checker for fbe, lbe, byte count etc..
 Implemented constraint for address mapping of pcie to axi
 Check Pcie2Axi path by sending vendor messages from Pcie to SES (SCSI enclosure
service, a SAS protocol)
 Develop pcie testcase for sending plx , non-plx vendor message
 Implementing checker and monitor for monitoring interrupt and checking messages by
using callback.](https://image.slidesharecdn.com/6092b113-2c06-4350-b02f-3669a4256276-170128080401/85/Somesh_Tessolve_updated-_resume-1-320.jpg)
![[2] PCIe Gen 4 :
Description: The avery VIP of PCIe Gen 4 was given. Task assigned to understand the
transaction layer protocol and run the related test cases.
Responsibilities:
 Went through the transaction layer protocols, packet formation, Buffer and ordering
flow control mechanism, error checking mechanism and ran the test cases respectively.
 Analyze the above testcases, debug and observe on waveform.
[3] Verification of AHB to APB Bridge using UVM
HDL: Verilog
HVL: SystemVerilog
TB Methodology: UVM
EDA Tools: Questasim and ISE
Description: The AHB to APB bridge is an AHB master and APB slave, providing an
interface between the high-speed AHB and the low-power APB. Read and write transfers on
the AHB are converted into equivalent transfers on the APB.
Responsibilities:
 Architected the class based verification environment using UVM
 Verified the RTL model using UVM testbench
 Generated functional and code coverage for the RTL verification
[4] Verification of Dual Port RAM using System Verilog
HDL: Verilog
EDA Tools: Questasim
TB Methodology: Constrained Randomized TB
Description:
 RTL design included integration of 4 dual port memory and 2 decoder for read and
write address.
 Design was verified using the System Verilog with functional and code
coverage.
 Formulating design from requirements, RTL coding, integration and debug of various
blocks, built SV TB components, integration with design
Responsibilities:
 Architected the design
 Checked the code coverage using Questasim
 Implemented code for functional Coverage
 Verified the RTL model using SystemVerilog.](https://image.slidesharecdn.com/6092b113-2c06-4350-b02f-3669a4256276-170128080401/85/Somesh_Tessolve_updated-_resume-2-320.jpg)
![ Generated functional and code coverage for the RTL verification
 Checked the code using assertion based verification
[5] Router 1x3 – RTL design and Verification
HDL: Verilog
HVL: SystemVerilog
TB Methodology: UVM
EDA Tools: Questasim and ISE
Description: The router accepts data packets on a single 8-bit port and routes them to one of
the three output channels, channel0, channel1 and channel2.
Responsibilities:
 Architected the design
 Implemented RTL using Verilog HDL.
 Architected the class based verification environment using UVM TB.
 Verified the RTL model using UVM TB.
 Generated functional and code coverage for the RTL verification
 Synthesized the design
Certifications:
Maven Silicon Certified Advanced VLSI Verification course
from Maven Silicon VLSI Design and Training Center, Bangalore June to August 2015
Orange Semiconductors, Bangalore: Undergone internship during Dec 15 -10 Jan 2014
GRID INDIA IT INNOVATIONS: Internship from 25th
May to July 25th
2014, Bangalore
Professional Qualification
Completed five year integrated B.Tech (ECE) + M.tech in VLSI from School of ICT,
Gautam Buddha University ,Greater Noida with 7.9 CGPA till last semester.
Personal Information:
Father’s Name: Satyanarayan Mishra
Date of Birth: 08-11- 1993
Place of Birth: Pondicherry
Gender: Male
Hobbies: Music, reading novels, tech surf etc..
Languages Known: English, Hindi, Oriya, Tamil](https://image.slidesharecdn.com/6092b113-2c06-4350-b02f-3669a4256276-170128080401/85/Somesh_Tessolve_updated-_resume-3-320.jpg)
Somesh_Tessolve_updated _resume
- 1. Somesh Mishra Tessolve Semiconductors Bhubaneswar Email: somesh.mishra@tessolve.com Odisha , India – 751013 Mobile: +91-9090965929 _______________________________________________________________________ VLSI Domain Skills HDL: Verilog HVL: SystemVerilog Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA TB Methodology: UVM EDA Tool: VCS, Verdi, DVT, Questasim, Modelsim, NCSim and ISE Domain: ASIC/FPGA Front-end Design and Verification Knowledge: RTL Coding, Simulation, Code Coverage, Functional Coverage, Synthesis, SVA Scripting language: Perl Experience Tessolve Semiconductors (Acquired Aims Technology Inc.) Jan 2016 – Current Maven Silicon VLSI Design and Verification Center, Bangalore June to August 2015 QSocs Technologies, August to Dec 2015 [1]Pcie2Axi and Axi2Pcie traffic: (Client Broadcom ) Description The axi transactions were converted to pcie transaction with internal addressing logics and inbound/outbound memory logics. Was given the task of generating axi to pcie traffic and vice versa and writing checker for few scenarios. Responsibilities:  In Axi2pcie path wrote testcase for Axi transfers and checker for pcie ,writing checker for wrap burst, writing checker for unaligned aligned addressing w.r.t pcie  Develop testcase to generate axi burst transfer, aligned and unaligned addressing.  Develop testcase for Wrap data transfer and writing checker for the unaligned addressing and wrap addressing. Writing Checker for pcie TL packets. Checked fbe, lbe, payload, address, th, tc etc..  Ran regression for axi to pcie path and done debugging.  Implementing checker for fbe, lbe, byte count etc..  Implemented constraint for address mapping of pcie to axi  Check Pcie2Axi path by sending vendor messages from Pcie to SES (SCSI enclosure service, a SAS protocol)  Develop pcie testcase for sending plx , non-plx vendor message  Implementing checker and monitor for monitoring interrupt and checking messages by using callback.
- 2. [2] PCIe Gen 4 : Description: The avery VIP of PCIe Gen 4 was given. Task assigned to understand the transaction layer protocol and run the related test cases. Responsibilities:  Went through the transaction layer protocols, packet formation, Buffer and ordering flow control mechanism, error checking mechanism and ran the test cases respectively.  Analyze the above testcases, debug and observe on waveform. [3] Verification of AHB to APB Bridge using UVM HDL: Verilog HVL: SystemVerilog TB Methodology: UVM EDA Tools: Questasim and ISE Description: The AHB to APB bridge is an AHB master and APB slave, providing an interface between the high-speed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB. Responsibilities:  Architected the class based verification environment using UVM  Verified the RTL model using UVM testbench  Generated functional and code coverage for the RTL verification [4] Verification of Dual Port RAM using System Verilog HDL: Verilog EDA Tools: Questasim TB Methodology: Constrained Randomized TB Description:  RTL design included integration of 4 dual port memory and 2 decoder for read and write address.  Design was verified using the System Verilog with functional and code coverage.  Formulating design from requirements, RTL coding, integration and debug of various blocks, built SV TB components, integration with design Responsibilities:  Architected the design  Checked the code coverage using Questasim  Implemented code for functional Coverage  Verified the RTL model using SystemVerilog.
- 3.  Generated functional and code coverage for the RTL verification  Checked the code using assertion based verification [5] Router 1x3 – RTL design and Verification HDL: Verilog HVL: SystemVerilog TB Methodology: UVM EDA Tools: Questasim and ISE Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2. Responsibilities:  Architected the design  Implemented RTL using Verilog HDL.  Architected the class based verification environment using UVM TB.  Verified the RTL model using UVM TB.  Generated functional and code coverage for the RTL verification  Synthesized the design Certifications: Maven Silicon Certified Advanced VLSI Verification course from Maven Silicon VLSI Design and Training Center, Bangalore June to August 2015 Orange Semiconductors, Bangalore: Undergone internship during Dec 15 -10 Jan 2014 GRID INDIA IT INNOVATIONS: Internship from 25th May to July 25th 2014, Bangalore Professional Qualification Completed five year integrated B.Tech (ECE) + M.tech in VLSI from School of ICT, Gautam Buddha University ,Greater Noida with 7.9 CGPA till last semester. Personal Information: Father’s Name: Satyanarayan Mishra Date of Birth: 08-11- 1993 Place of Birth: Pondicherry Gender: Male Hobbies: Music, reading novels, tech surf etc.. Languages Known: English, Hindi, Oriya, Tamil