11. 3. CPU SW correlates received samples with expected PSS to get slot timing
4. CPU SW correlates received samples with expected SSS to get 10 ms frame
timing
12. 5. CPU SW decodes MIB using convert_mib() in sib_decoder.c
MIB ? ??? ??? ?? 40 ms ?? ????.
6. CPU SW get SFN, BW, cell ID info from MIB
13. MIB ? ??? ?? ??? ????.
7. CPU SW get SIB scheduling info from SIB 1
SIB 1 ? ??? ?? ?? SIB ? ???? ??? ??? ??.
8. CPU SW get RACH info from SIB 2
SIB 2 ? ??? ?? UL RACH ?? ??? ????.
i) Access Barring Information - Access Probability factor, Access Class Baring List,
Access Class Baring Time
ii) Semi static Common Channel Configuration - Random Access Parameter,
PRACH Configuration
iii) UL frequency Information - UL EARFCN, UL Bandwidth, additional emmission
iv) MBSFN Configuration
14. 7. CPU SW decides 1 s timing from SFN
8. CPU SW assert interrupt to 1PPS via GPIO to adjust timing for next operation
5 PRACH ??? ??? ?? ????
3GPP 36.902 4.7 ? ??? RACH ??? ??? ?? ????? ??? ??.
PRACH Configuration Index
??? PRACH ? ?? sub-frame ?? ?????? ???? ?????
??? ??? ??? ??.
- access probability
- access delay probability
- PUSCH load
PRACH Transmission Power Control Parameters
??? ?? ??? ?? ???? PRACH ? ?? ???? ????
????? ??? ??? ??? ??. UL ??? ??? ?? ??? ??
??? ????.
- access probability