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Sreedhar_Resume

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A.R. Sreedhar has a M.Tech in VLSI Design from NIT-Warangal and a B.Tech in ECE from JNTU College of Engineering. He has work experience as an intern at SM Silicon India Pvt. Ltd. working on CPU core verification. His M.Tech dissertation was on a low power SAR ADC for biomedical applications consuming less than 1uW at 1KSPS and 10-bit resolution. He has experience designing analog and digital circuits using tools like Cadence Virtuoso and Xilinx ISE. He has strengths in digital logic design, Verilog/VHDL, and analog circuit design skills.

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A.R.SREEDHAR Email: sreedharjntuece@gmail.com Mobile: 08886590580 ACADEMIC PROFILE : Degree Board / University Year CGPA / Percentage M.Tech [VLSI Design] NIT-WARANGAL 2013 - 2015 7.69 B.Tech [ECE] JNTU College of Engg Pulivendula 2007 - 2011 67.27% Intermediate NARAYANA JR COLLEGE,Anantapur 2005-2007 92.7% SSC Little Flower Montessori High School, Anantapur 2004-2005 84.16% WORKING EXPERIENCE : Intern in SM SILICON INDIA PVT.LTD. Hyderabad. Member of CPU CORE VERIFICATION team working on the issues related to failures in RTL, debugging the Test issues. M. TECH. DISSERTATION : Design of 1KS/s, 10 Bit Low Power SAR ADC for Biomedical Application Abstract: Low-energy successive approximation ADC targeted for use in Biomedical Application is presented. Energy is extremely limited, forcing the ADC to operate with very little energy per sample. This work describes the design and implementation of an ADC to meet the unique requirements of pace maker. The ADC consumes less than 1uW at 1 V supply at a speed of 1KSPS with 10 bits of resolution. Tool used: Cadence Virtuoso. PROJECTS : Designed An Optimally Compensated OP-AMP in Cadence Virtuoso for Gain -50,000 , UGB-1GHz and Phase margin-600 and Slew Rate- 2V/us by factoring other design constraints. Designed basic analog building blocks of Analog IC (single stage amplifiers, current & voltage references). Designed a Pipelined unsigned integer 8-BIT MAC UNIT for Throughput=1MAC/cycle, Delay < 20ns in Xilinx ISE using VHDL for computation in Digital signal processors.
TECHNICAL SKILLS : RELEVANT COURSE WORK : - Analog Integrated Circuit Design, Digital Integrated Circuit Design , Mixed Signal Design, Advanced Computer Architecture - Digital VLSI Testing and Testability, Low Power CMOS VLSI, VLSI Physical Design & Automation, Device Modeling. CORE COMPETENCY : - Good knowledge in Digital Logic Design. - Exposure to programming in Verilog HDL. - Hands on experience in designing analog circuits using Cadence Virtuoso IC615, SPECTRE. ACADEMIC ACHIEVEMENTS : - Secured 1127 Rank in Gate 2012(99.36 percentile). - Secured 2438 Rank in EAMCET (Engineering Entrance Exam in AP) 2007. - Consistently scored 100% marks in 10th and 12th standard Mathematics. PERSONAL STRENGTHS : - Hard working and good at team work. - Positive attitude and adaptability. EXTRA CURRICULAR ACTIVITIES : - Worked as placement coordinator for M.Tech-VLSI. - Worked as member of E-CHIP (Department organization) in B.Tech. - Member of school cricket team. Declaration: I hereby declare that the above mentioned details are true to the best of my knowledge. Tools: Languages: CADENCE-VIRTUOSO C Xilinx ISE Design Suite Verilog , VHDL Tanner Tools Synopsys HSPICE

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  • 1. A.R.SREEDHAR Email: sreedharjntuece@gmail.com Mobile: 08886590580 ACADEMIC PROFILE : Degree Board / University Year CGPA / Percentage M.Tech [VLSI Design] NIT-WARANGAL 2013 - 2015 7.69 B.Tech [ECE] JNTU College of Engg Pulivendula 2007 - 2011 67.27% Intermediate NARAYANA JR COLLEGE,Anantapur 2005-2007 92.7% SSC Little Flower Montessori High School, Anantapur 2004-2005 84.16% WORKING EXPERIENCE : Intern in SM SILICON INDIA PVT.LTD. Hyderabad. Member of CPU CORE VERIFICATION team working on the issues related to failures in RTL, debugging the Test issues. M. TECH. DISSERTATION : Design of 1KS/s, 10 Bit Low Power SAR ADC for Biomedical Application Abstract: Low-energy successive approximation ADC targeted for use in Biomedical Application is presented. Energy is extremely limited, forcing the ADC to operate with very little energy per sample. This work describes the design and implementation of an ADC to meet the unique requirements of pace maker. The ADC consumes less than 1uW at 1 V supply at a speed of 1KSPS with 10 bits of resolution. Tool used: Cadence Virtuoso. PROJECTS : Designed An Optimally Compensated OP-AMP in Cadence Virtuoso for Gain -50,000 , UGB-1GHz and Phase margin-600 and Slew Rate- 2V/us by factoring other design constraints. Designed basic analog building blocks of Analog IC (single stage amplifiers, current & voltage references). Designed a Pipelined unsigned integer 8-BIT MAC UNIT for Throughput=1MAC/cycle, Delay < 20ns in Xilinx ISE using VHDL for computation in Digital signal processors.
  • 2. TECHNICAL SKILLS : RELEVANT COURSE WORK : - Analog Integrated Circuit Design, Digital Integrated Circuit Design , Mixed Signal Design, Advanced Computer Architecture - Digital VLSI Testing and Testability, Low Power CMOS VLSI, VLSI Physical Design & Automation, Device Modeling. CORE COMPETENCY : - Good knowledge in Digital Logic Design. - Exposure to programming in Verilog HDL. - Hands on experience in designing analog circuits using Cadence Virtuoso IC615, SPECTRE. ACADEMIC ACHIEVEMENTS : - Secured 1127 Rank in Gate 2012(99.36 percentile). - Secured 2438 Rank in EAMCET (Engineering Entrance Exam in AP) 2007. - Consistently scored 100% marks in 10th and 12th standard Mathematics. PERSONAL STRENGTHS : - Hard working and good at team work. - Positive attitude and adaptability. EXTRA CURRICULAR ACTIVITIES : - Worked as placement coordinator for M.Tech-VLSI. - Worked as member of E-CHIP (Department organization) in B.Tech. - Member of school cricket team. Declaration: I hereby declare that the above mentioned details are true to the best of my knowledge. Tools: Languages: CADENCE-VIRTUOSO C Xilinx ISE Design Suite Verilog , VHDL Tanner Tools Synopsys HSPICE