The document shows a diagram of a microprocessor with an address bus that is split into a higher address bus and lower address bus. The higher address bus connects to address lines A15-A8 and the lower address bus connects to address lines A7-A0. An 74373 latch receives the lower address and three-state buffers it onto the lower address bus under the control of the ALE signal. This allows separating the address bus to access wider memory.