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Full Adder in Dataflow model:
Code:
module fulladder(
input a,
input b,
input cin,
output s,
output cout
);
assign s=a^b^cin;
assign cout=(a & b) | cin & (a ^ b);
endmodule
Output:
RTL Schematic:
Hardware:
Verilog full adder in dataflow  & gate level modelling style.
Full Adder in Gate level model :
Code:
module fa(
input a,
input b,
input cin,
output s,
output cout
);
wire x1,x2,x3;
xor(x1,a,b);
and(x3,a,b);
xor(s,x1,cin);
and(x2,x1,cin);
or(cout,x2,x3);
endmodule
Output:
RTL Schematic:

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Verilog full adder in dataflow & gate level modelling style.

  • 1. Full Adder in Dataflow model: Code: module fulladder( input a, input b, input cin, output s, output cout ); assign s=a^b^cin; assign cout=(a & b) | cin & (a ^ b); endmodule Output:
  • 5. Full Adder in Gate level model : Code: module fa( input a, input b, input cin, output s, output cout ); wire x1,x2,x3; xor(x1,a,b); and(x3,a,b); xor(s,x1,cin); and(x2,x1,cin); or(cout,x2,x3); endmodule Output: