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VINOD_KAMALAPUR_RESUME (1)

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vinod kamalapur

Vinod Kamalapur is seeking an opportunity as a product engineer with experience in image sensor validation. He has a B.E. in electronics and communication and is undergoing advanced training in design and verification. He has published a paper on designing complex multipliers using Vedic mathematics and has experience undertaking projects involving UART IP core verification, router design/verification, and implementing cryptographic algorithms on FPGAs. His skills include Verilog HDL, UVM methodology, and using EDA tools for design and verification.

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Mr. VINOD KAMALAPUR. E-mail: kamalapur438@gmail.com Mobile: +91-9916336299. CAREER OBJECTIVE To be the significant contributor in the chosen field for the growth of the company, and be counted amongst the top few technologists in the ever-growing industry. Being strong believer in symbiotic approach, I would also like to take an initiative, innovate newer processes for the amelioration of the company. INTERNSHIP Working for ON SEMICONDUCTOR as Product Engineer, Validation for Image Sensors. ACADEMICS Undergoing Advance training in Maven Silicon Pvt. Ltd. Bangalore on Design and Verification. B.E in Electronics and Communication from Sri Dharmasthala Manjunatheshwara College of Engineering & Technology Dharwad, Affiliated by Visvesvaraya Technological University, Belagavi. With CGPA: 7.54 in 2015. Diploma in Electronics & Communication from Government Polytechnic College Kalaburagi., with 61.68% marks. PAPER PUBLICATION Presented a paper titled A Novel Approach to Design Complex Multiplier using Vedic Sutras at International Conference on Circuits, Communication, Control and Computing - I4C2014, sponsored by IEEE, Print ISBN: 978-1-4799-6545-8, held in M.S. Ramaiah Institute of Technology Bengaluru, dated on 21-11-2014. PROJECTS UNDERTAKEN UART- IP Core Verification using UVM methodology. Description: The UART IP core provides serial communication capabilities, which allow communication with modem or other external devices. UART will operate in three different modes Simplex mode, Full Duplex mode and loopback mode. Design and Implementation of Router 1X3 and its verification using UVM. Description: In this Router 1x3 means Router contains one input source and three destination output channels. The input source will forward the data packets to any one of the destination output channel based on the address. Before sending packets to destination channels, data
packets are stored in FIFOS. I have written RTL code for router based on input and output protocol and verified using System Verilog. Efficient Implementation of Cryptographic Algorithms Using Re-Configurable Computing Systems. (Final year major project) Description: Aim of project is to implement cryptographic algorithms in hardware platform such as FPGAs which are cost effective and highly secured. Design and Implementation of Complex Multiplier Using Vedic Sutras. (6th semester mini project) Description: The main aim of the project is to improve the speed of the multiplication of a complex number using Vedic Sutras. The modeling of the solution is done using the Simulink block sets and functional verification is performed using Xilinx ISE tool. Embedded Based complete solution for form Irrigation using voice message through GSM Network. (Diploma Final year project) The main aim of the project is to control the motor, which is installed in the field, operation (synchronizing with GSM Modem) through Mobile phones. SKILLS:- Digital Electronics, Verilog HDL, Reconfigurable Computing, UVM. Experience in using industry standard EDA tools for the front-end design and verification. Basics of CMOS & Layout Techniques Basic knowledge of designing various layouts by using CMOS standard processes. Languages Assembly Languages ( 8051), Verilog HDL, System Verilog, Basics of C. Tools Microcap, Eagle P.C.B., Kiel, Matlab, Simulink, Xilinx, Cadence, Riviera-PRO, Questa SIM. CO-CURRICULAR ACTIVITIES:- Completed Internship on Telecommunication System and Networks at Southern Telecom Sub Region, Hubballi during 29-12-2014 to 03-01-2015. Participated as a volunteer in ROBOCON INDIA-2012 competition, a National level event conducted in M.I.T. Pune year-2013. Participated in "DO IT YOURSELF-2009", a state level project competition held in Kalaburagi year 2008-09. PERSONAL DETAILS Fathers Name Mr. Sanna Veeranna Kamalapur Mothers Name Mrs. Geetha Kamalapur Date of Birth 28th Oct 1989 Gender Male Passport Number J1403059 Languages known Kannada, Hindi, Telugu and English.
Place: Bangalore. (Vinod Kamalapur)

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VINOD_KAMALAPUR_RESUME (1)

  • 1. Mr. VINOD KAMALAPUR. E-mail: kamalapur438@gmail.com Mobile: +91-9916336299. CAREER OBJECTIVE To be the significant contributor in the chosen field for the growth of the company, and be counted amongst the top few technologists in the ever-growing industry. Being strong believer in symbiotic approach, I would also like to take an initiative, innovate newer processes for the amelioration of the company. INTERNSHIP Working for ON SEMICONDUCTOR as Product Engineer, Validation for Image Sensors. ACADEMICS Undergoing Advance training in Maven Silicon Pvt. Ltd. Bangalore on Design and Verification. B.E in Electronics and Communication from Sri Dharmasthala Manjunatheshwara College of Engineering & Technology Dharwad, Affiliated by Visvesvaraya Technological University, Belagavi. With CGPA: 7.54 in 2015. Diploma in Electronics & Communication from Government Polytechnic College Kalaburagi., with 61.68% marks. PAPER PUBLICATION Presented a paper titled A Novel Approach to Design Complex Multiplier using Vedic Sutras at International Conference on Circuits, Communication, Control and Computing - I4C2014, sponsored by IEEE, Print ISBN: 978-1-4799-6545-8, held in M.S. Ramaiah Institute of Technology Bengaluru, dated on 21-11-2014. PROJECTS UNDERTAKEN UART- IP Core Verification using UVM methodology. Description: The UART IP core provides serial communication capabilities, which allow communication with modem or other external devices. UART will operate in three different modes Simplex mode, Full Duplex mode and loopback mode. Design and Implementation of Router 1X3 and its verification using UVM. Description: In this Router 1x3 means Router contains one input source and three destination output channels. The input source will forward the data packets to any one of the destination output channel based on the address. Before sending packets to destination channels, data
  • 2. packets are stored in FIFOS. I have written RTL code for router based on input and output protocol and verified using System Verilog. Efficient Implementation of Cryptographic Algorithms Using Re-Configurable Computing Systems. (Final year major project) Description: Aim of project is to implement cryptographic algorithms in hardware platform such as FPGAs which are cost effective and highly secured. Design and Implementation of Complex Multiplier Using Vedic Sutras. (6th semester mini project) Description: The main aim of the project is to improve the speed of the multiplication of a complex number using Vedic Sutras. The modeling of the solution is done using the Simulink block sets and functional verification is performed using Xilinx ISE tool. Embedded Based complete solution for form Irrigation using voice message through GSM Network. (Diploma Final year project) The main aim of the project is to control the motor, which is installed in the field, operation (synchronizing with GSM Modem) through Mobile phones. SKILLS:- Digital Electronics, Verilog HDL, Reconfigurable Computing, UVM. Experience in using industry standard EDA tools for the front-end design and verification. Basics of CMOS & Layout Techniques Basic knowledge of designing various layouts by using CMOS standard processes. Languages Assembly Languages ( 8051), Verilog HDL, System Verilog, Basics of C. Tools Microcap, Eagle P.C.B., Kiel, Matlab, Simulink, Xilinx, Cadence, Riviera-PRO, Questa SIM. CO-CURRICULAR ACTIVITIES:- Completed Internship on Telecommunication System and Networks at Southern Telecom Sub Region, Hubballi during 29-12-2014 to 03-01-2015. Participated as a volunteer in ROBOCON INDIA-2012 competition, a National level event conducted in M.I.T. Pune year-2013. Participated in "DO IT YOURSELF-2009", a state level project competition held in Kalaburagi year 2008-09. PERSONAL DETAILS Fathers Name Mr. Sanna Veeranna Kamalapur Mothers Name Mrs. Geetha Kamalapur Date of Birth 28th Oct 1989 Gender Male Passport Number J1403059 Languages known Kannada, Hindi, Telugu and English.