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Vlsi(2)

Rritu Bhagat
Rritu Bhagat

This presentation summarizes VLSI and VHDL. VLSI refers to integrating millions of transistors on a single chip. VHDL stands for Very High Speed Integrated Circuit Hardware Description Language and is used to model digital circuits. The VHDL design flow involves specification, HDL entry, functional simulation, timing simulation, and synthesis. VHDL code structure includes libraries, entities that declare I/O ports, and architectures that describe circuit behavior. VHDL can model circuits structurally, using a data flow approach with concurrent statements, or behaviorally using sequential statements in processes.

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PRESENTATION ON VLSI Yamuna Institute of Engineering and Technology Submitted by Ritu Kumari 4109263
VLSI VERY LARGE SCALED INTIGRATING 束 VLSI Is the science of integrating millions of transistor on a Single chip 損 Operating devices: CPLD FPGA
VHDL VHDL Stands for V 束 V : Very H : High S : Speed I : Integrated C : Circuit H Hardware D Designing L Language
Features of VHDL Support for concurrent statements Waveform generation language Sequential statements
VHDL DESIGN FLOW Functional Simulation Specification HDL Entry Timing Simulation Simulation Synthesis Implementation
VHDL CODE STRUCTURE
LIBRARY declarations:-Contains a list of all libraries to be used in the design, e.g.: ieee, std, work, etc. ENTITY:-Specifies the I/O pins of the circuit . ARCHITECTURE:-Contains the VHDL code proper, which describes how the circuit should behave (function).
LIBRARY A LIBRARY is a collection of commonly used pieces of code. SYNTAX:- LIBRARY library_name; USE library_name.package_name.package_parts; ieee.std_logic_1164 (from the ieee library) standard (from the std library) work (from the work library)
ENTITY The Primary Purpose of an Entity Is to Declare the Input and Output Signals Which Communicate With It. SYNTAX:- ENTITY entity_name IS PORT ( port_name : signal_mode signal_type; port_name : signal_mode signal_type; ... ); END entity_name;
ARCHITECTURE Architecture body specifies how the circuit operated and how it is implemented. SYNTAX:- ARCHITECTURE architecture name OF entity_name IS [declarations] BEGIN (code) END architecture_name;
OPERATORS Assignment Operators Logical Operators Arithmetic Operators Relational operators Shift Operators
Class 1. Logical operators And Or nand nor xor xnor 2. Relational operators = /= < <= > >= 3. Shift operators sll srl sla sra rol ror 4. Assignment operator <= := >= 5.Addition operator + _ & 6. Multiplying operator * / mod rem 7.Miscellaneous operator ** abs not
VHDL can be structured in three different ways Structural As a set of interconnected components Data flow As a set of concurrent statements Behavioral As a set of sequential statements
DATA FLOW Data flow describes how the data flows through the circuit, from input to output. Use concurrent statement. CONCURRENT STATEMENT Executed at once. combinational logic circuits are build with concurrent code. Three types of concurrent statements used in dataflow descriptions Boolean Equations with-select-when when-else
BEHAVIORAL MODELING To model complex components More powerful and allows for easy implementation of the design supported inside a process statement SYNTAX:- [label:] PROCESS (sensitivity list) [VARIABLE name type [range] [:= initial_value;]] BEGIN (sequential code) END PROCESS [label];
STRUCTURAL MODELING Structural description uses text to show how components of circuit put together Structural modeling use SEQUENTIAL STATEMENTS SEQUENTIAL STATEMENTS If Case Wait Loop
LCD Display on using serial communication
WORKING COMPUTER CPLD TTL logic 0=0v 1=3.3v RS 232 level logic 0= +3v to +15 v Max 232 1= -3v to -15 Voltage level convertor LCD Serial communication Parallel communication
Vlsi(2)
Vlsi(2)

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Vlsi(2)

  • 1. PRESENTATION ON VLSI Yamuna Institute of Engineering and Technology Submitted by Ritu Kumari 4109263
  • 2. VLSI VERY LARGE SCALED INTIGRATING 束 VLSI Is the science of integrating millions of transistor on a Single chip 損 Operating devices: CPLD FPGA
  • 3. VHDL VHDL Stands for V 束 V : Very H : High S : Speed I : Integrated C : Circuit H Hardware D Designing L Language
  • 4. Features of VHDL Support for concurrent statements Waveform generation language Sequential statements
  • 5. VHDL DESIGN FLOW Functional Simulation Specification HDL Entry Timing Simulation Simulation Synthesis Implementation
  • 7. LIBRARY declarations:-Contains a list of all libraries to be used in the design, e.g.: ieee, std, work, etc. ENTITY:-Specifies the I/O pins of the circuit . ARCHITECTURE:-Contains the VHDL code proper, which describes how the circuit should behave (function).
  • 8. LIBRARY A LIBRARY is a collection of commonly used pieces of code. SYNTAX:- LIBRARY library_name; USE library_name.package_name.package_parts; ieee.std_logic_1164 (from the ieee library) standard (from the std library) work (from the work library)
  • 9. ENTITY The Primary Purpose of an Entity Is to Declare the Input and Output Signals Which Communicate With It. SYNTAX:- ENTITY entity_name IS PORT ( port_name : signal_mode signal_type; port_name : signal_mode signal_type; ... ); END entity_name;
  • 10. ARCHITECTURE Architecture body specifies how the circuit operated and how it is implemented. SYNTAX:- ARCHITECTURE architecture name OF entity_name IS [declarations] BEGIN (code) END architecture_name;
  • 11. OPERATORS Assignment Operators Logical Operators Arithmetic Operators Relational operators Shift Operators
  • 12. Class 1. Logical operators And Or nand nor xor xnor 2. Relational operators = /= < <= > >= 3. Shift operators sll srl sla sra rol ror 4. Assignment operator <= := >= 5.Addition operator + _ & 6. Multiplying operator * / mod rem 7.Miscellaneous operator ** abs not
  • 13. VHDL can be structured in three different ways Structural As a set of interconnected components Data flow As a set of concurrent statements Behavioral As a set of sequential statements
  • 14. DATA FLOW Data flow describes how the data flows through the circuit, from input to output. Use concurrent statement. CONCURRENT STATEMENT Executed at once. combinational logic circuits are build with concurrent code. Three types of concurrent statements used in dataflow descriptions Boolean Equations with-select-when when-else
  • 15. BEHAVIORAL MODELING To model complex components More powerful and allows for easy implementation of the design supported inside a process statement SYNTAX:- [label:] PROCESS (sensitivity list) [VARIABLE name type [range] [:= initial_value;]] BEGIN (sequential code) END PROCESS [label];
  • 16. STRUCTURAL MODELING Structural description uses text to show how components of circuit put together Structural modeling use SEQUENTIAL STATEMENTS SEQUENTIAL STATEMENTS If Case Wait Loop
  • 17. LCD Display on using serial communication
  • 18. WORKING COMPUTER CPLD TTL logic 0=0v 1=3.3v RS 232 level logic 0= +3v to +15 v Max 232 1= -3v to -15 Voltage level convertor LCD Serial communication Parallel communication