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- 2. Unit-IV Gate Level Design: Switch logic, Pass transistors, transmission gates alternate gate circuits, Pseudo- NMOS logic, Differential Cascaded Voltage Static logic (DCVS) logic, Dynamic logic, Domino logic, Clocked CMOS logic, Low power gates.
- 3. Subsystem Design (Guide Lines to be Followed)
- 4. Take, for example, the case of a relatively straightforward MSI logic circuit comprising, say, 500 transistors. A reasonable time to allocate to the design and proving of such a circuit could be some two engineer months. Consider now the design of a 500,000 transistor VLSI system. Even if a linear relationship exists between complexity and design time, the required design time would be 2000 engineer-months or 170 engineer-years.
- 5. 1. Define the requirements (properly and carefully). 2. Partition the overall architecture into appropriate subsystems. 3. Consider communication paths carefully in order to develop sensible interrelationships between subsystems. 4. Draw a floor plan of how the system is to map onto the silicon (and alternate between 2, 3 and 4 as necessary).
- 6. 5. Aim for regular structures so that design is largely a matter of replication. 6. Draw suitable (stick or symbolic) diagrams of the leaf-cells of the subsystems. 7. Convert each cell to a layout. 8. Carefully and thoroughly carry out a design rule check on each cell. 9. Simulate the performance of each cell/subsystem.
- 7. Switch logic is based on the 'pass transistor' or on transmission gates. This approach is fast for small arrays and takes no static current from the supply rails. Thus, power dissipation of such arrays is small since current only flows on switching.
- 8. Switch (pass transistor) logic is similar to logic arrays based on relay contacts in that the path through each switch is isolated from the signal activating the switch. In consequence, the designer has a considerable amount of freedom in implementing architectural features compared with bipolar logic-based designs.
- 10. n-MOS transistor/ switch produces Strong 0 but weak 1
- 11. p-MOS transistor/ switch produces Strong 1 but weak 0
- 12. Transmission gate produces Strong both strong1 and strong 0.
- 14. 2 Input NAND GATE (using n-MOS & CMOS Logic)
- 15. Other Forms of CMOS Logic
- 16. Pseudo- NMOS logic Dynamic logic Domino logic Clocked CMOS logic Differential Cascaded Voltage Static logic (DCVS) logic
- 18. Clearly, if we replace the depletion mode pull-up transistor of the standard nMOS circuits with a p- transistor with gate connected to Vss, we have a structure similar to the nMOS equivalent. 1.Power dissipation is reduced to about 60% of that associated with the comparable nMOS device. 2. Owing to the higher pull-up resistance, the inverter pair delay is larger by a factor of 8.5:5 than the 4:1 minimum size nMOS inverter.
- 19. Dynamic CMOS logic 陸=0, pre charge stage 陸=1, evaluation stage 3 Input NAND GATE
- 20. The actual logic is implemented in the inherently faster nMOS logic (the n-block); a p-transistor is used for the non-time-critical precharging of the output line 'Z' so that the output capacitance is charged to V DD during the off period of the clock signal . During this same period the inputs are applied to the n- block and the state of the logic is then evaluated during the on period of the clock when the bottom n-transistor is turned on.
- 21. The output voltage level is stored in a capacitor during the precharge phase of the clock cycle, and then evaluated during the evaluation phase. Dynamic CMOS logic has high speed, low area, and simple layout. However, it also has some challenges, such as high power dissipation, low noise margin, and low fan-out.
- 25. Advantages of Clocked CMOS Logic Predictable Timing Simplified Sequential Design Ease of Design and Debugging Improved Signal Integrity Disadvantages of Clocked CMOS Logic Increased Power Consumption Clock Skew and Jitter Area Overhead Latency Design Complexity
- 28. 2 INPUT NAND GATE
- 29. 1. Such logic structures can have smaller areas than conventional CMOS logic. 2. Parasitic capacitances are smaller so that higher operating speeds are possible. 3. Operation is free of glitches since each gate can make only one '1' to '0' transition. 4. Only non-inverting structures are possible because of the presence of the inverting buffer. 5. Charge distribution may be a problem and must be considered.
- 30. DCVS Logic DCVS - Differential Cascode Voltage Switch Differential inputs, outputs Two pulldown networks Tradeoffs Lower capacitative loading than static CMOS No ratioed logic needed Low static power consumption More transistors More signals to route between gates OUT Pulldown Network OUT OUT Pulldown Network OUT A B C A B C
- 32. Advantages of DCVS Logic High-Speed Operation Low Power Consumption Reduced Noise Sensitivity Better Signal Integrity Disadvantages of DCVS Logic Increased Complexity Design complexity/Area overhead
- 33. Low Power Gates
- 34. Introduction Definition: What are low power gates? Importance: Why is low power design crucial in modern electronics? Power Consumption in Digital Circuits Dynamic Power Consumption: Switching activity, capacitive load Static Power Consumption: Leakage currents, subthreshold leakage
- 35. Techniques for Low Power Design Voltage Scaling: Lowering supply voltage Clock Gating: Reducing clock signal to idle portions of the circuit Power Gating: Shutting off power to inactive blocks Multi-Threshold CMOS (MTCMOS): Using transistors with different threshold voltage
- 36. Types of Low Power Gates Standard CMOS Gates: Basic CMOS inverter, NAND, NOR Sub-threshold Gates: Operating at voltages below the threshold voltage Adiabatic Logic Gates: Energy recovery logic FinFET Technology: Reducing leakage current and dynamic power
- 37. A FinFET is a type of field-effect transistor (FET) that has a thin vertical fin instead of being completely planar. The gate is fully wrapped around the channel on three sides formed between the source and the drain.
- 38. Planar transistors vs. finFETs vs. gate-all-around Source: Lam Research