![[Giao trinh] vi dieu-khien_8051 - dh tra vinh](https://cdn.slidesharecdn.com/ss_thumbnails/giaotrinh-vidieukhien8051-dhtravinh-140114075729-phpapp02-thumbnail.jpg?width=560&fit=bounds)
More Related Content
What's hot (20)
Similar to Vxl ch03-8051-3.1 3.2-v03 (20)
More from Huynh MVT (20)
Recently uploaded (18)
![[PPT11] Bi 7 - 畛c - C Mau qu棚 x畛.pptx](https://cdn.slidesharecdn.com/ss_thumbnails/ppt11bi7-c-cmauqux-250305070313-62766c8d-thumbnail.jpg?width=560&fit=bounds)
![[PPT11] Bi 7 - 畛c - V t担i v畉n mu畛n m畉....ppt](https://cdn.slidesharecdn.com/ss_thumbnails/ppt11bi7-c-vtivnmunm-250305063122-6e221a47-thumbnail.jpg?width=560&fit=bounds)
Vxl ch03-8051-3.1 3.2-v03
- 1. H畛 VI I畛U KHI畛N 8051 1 Hi畛u 鱈nh t畛 slide c畛a th畉y H畛 Trung M畛 B畛 m担n i畛n t畛 - DH BK TPHCM
- 2. N畛i dung 3.1 Gi畛i thi畛u h畛 vi i畛u khi畛n 8051 3.2 Ki畉n tr炭c ph畉n c畛ng 8051 2
- 3. 3.1 Gi畛i thi畛u h畛 vi i畛u khi畛n 8051 3
- 4. C叩c ki畉n tr炭c vi i畛u khi畛n 4 CPU Program + Data Address Bus Data Bus Memory Von Neumann Architecture CPU Program Address Bus Data Bus Harvard Architecture Memory Data Address Bus Fetch Bus 0 0 0 2n
- 5. H畛 VK 8051 8051 l vi i畛u khi畛n 畉u ti棚n c畛a h畛 vi i畛u khi畛n MCS51 動畛c Intel s畉n xu畉t vo nm 1980. H畛 MCS51 l h畛 8-bit c坦 kh畉 nng 畛nh 畛a ch畛 64KB b畛 nh畛 ch動董ng tr狸nh v 64KB b畛 nh畛 d畛 li畛u. 5
- 6. So So s叩nh s叩nh c叩c c叩c d嘆ng d嘆ng MCS MCS- -51 51 6 3 256 bytes 8K EPROM 8752 3 256 bytes 0K 8032 3 256 bytes 8K ROM 8052 2 128 bytes 4K EPROM 8751 2 128 bytes 0K 8031 2 128 bytes 4K ROM 8051 Timers On-Chip Data Memory On-Chip Code Memory Part Number
- 7. 3.2 Ki畉n tr炭c ph畉n c畛ng 8051 7
- 8. 3.2.1 S董 畛 kh畛i 8051/8031 8
- 9. 9
- 10. ngh挑a c叩c ch但n tr棚n MCU 8051 Port 0 (C畛ng 0) Port 0 l m畛t port hai ch畛c nng tr棚n c叩c ch但n 3239. Trong c叩c thi畉t k畉 c畛 nh畛 (kh担ng d湛ng b畛 nh畛 m畛 r畛ng) n坦 c坦 ch畛c nng nh動 c叩c 動畛ng I/O. 畛i v畛i c叩c thi畉t k畉 l畛n v畛i b畛 nh畛 m畛 r畛ng, n坦 動畛c d畛n k棚nh gi畛a bus 畛a ch畛 v bus d畛 li畛u. Port 1 (C畛ng 1) Port 1 l c畛ng dnh ri棚ng cho nh畉p/xu畉t tr棚n c叩c ch但n 18. C叩c ch但n 動畛c k箪 hi畛u P1.0, P1.1, P1.2, ... c坦 th畛 d湛ng cho giao ti畉p v畛i c叩c thi畉t b畛 ngoi n畉u c畉n. Port 1 kh担ng c坦 ch畛c nng kh叩c, v狸 v畉y ch炭ng ch畛 動畛c d湛ng cho giao ti畉p v畛i c叩c thi畉t b畛 ngoi. Port 2 (C畛ng 2) Port 2 l m畛t c畛ng c担ng d畛ng k辿p tr棚n c叩c ch但n 2128 動畛c d湛ng nh動 c叩c 動畛ng xu畉t nh畉p ho畉c l byte cao c畛a bus 畛a ch畛 畛i v畛i c叩c thi畉t k畉 d湛ng b畛 nh畛 m畛 r畛ng. Port 3 (C畛ng 3) Port 3 c滴ng l m畛t c畛ng c担ng d畛ng k辿p tr棚n c叩c ch但n 1017. C叩c ch但n c畛a port ny c坦 nhi畛u ch畛c nng, c叩c c担ng d畛ng chuy畛n 畛i c坦 li棚n h畛 v畛i c叩c 畉c t鱈nh 畉c bi畛t c畛a 8051/8031 10
- 11. C叩c ch畛c nng chuy畛n 畛i 畛 Port 3 11
- 12. 12
- 13. 3.2.2 C畉u tr炭c c畛ng I/O Kh畉 nng l叩i l 4 t畉i TTL lo畉i LS (Low Power Schottky) v畛i c叩c c畛ng P1, P2, v P3; v 8 t畉i TTL lo畉i LS v畛i c畛ng P0. Ch炭 箪 l i畛n tr畛 k辿o l棚n b棚n trong kh担ng c坦 trong Port 0 (ngo畉i tr畛 l炭c lm vi畛c nh動 bus d畛 li畛u / 畛a ch畛 b棚n ngoi). i畛n tr畛 k辿o l棚n c坦 th畛 動畛c s畛 d畛ng v畛i P0 t湛y theo 畉c t鱈nh vo c畛a thi畉t b畛 m n坦 l叩i. 13
- 14. 14
- 15. 15
- 16. A Pin of Port 1 16 8051 IC D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X TB1 TB2 P0.x
- 17. Writing 1 to Output Pin P1.X 17 D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X 8051 IC 2. output pin is Vcc 1. write a 1 to the pin 1 0 output 1 TB1 TB2
- 18. Writing 0 to Output Pin P1.X 18 D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X 8051 IC 2. output pin is ground 1. write a 0 to the pin 0 1 output 0 TB1 TB2
- 19. Reading High at Input Pin 19 D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X 8051 IC 2. MOV A,P1 external pin=High 1. write a 1 to the pin MOV P1,#0FFH 1 0 3. Read pin=1 Read latch=0 Write to latch=1 1 TB1 TB2
- 20. Reading Low at Input Pin 20 D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X 8051 IC 2. MOV A,P1 external pin=Low 1. write a 1 to the pin MOV P1,#0FFH 1 0 3. Read pin=1 Read latch=0 Write to latch=1 0 TB1 TB2
- 21. Other Pins P1, P2, and P3 have internal pull-up resisters. P1, P2, and P3 are not open drain. P0 has no internal pull-up resistors and does not connects to Vcc inside the 8051. P0 is open drain. Compare the figures of P1.X and P0.X. However, for a programmer, it is the same to program P0, P1, P2 and P3. All the ports upon RESET are configured as output. 21
- 22. A Pin of Port 0 22 8051 IC D Q Clk Q Read latch Read pin Write to latch Internal CPU bus M1 P0.X pin P1.X TB1 TB2 P1.x
- 23. Port 0 with Pull-Up Resistors 23 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 DS5000 8751 8951 Vcc 10 K Port 0
- 24. Port 3 Alternate Functions 24 17 RD P3.7 16 WR P3.6 15 T1 P3.5 14 T0 P3.4 13 INT1 P3.3 12 INT0 P3.2 11 TxD P3.1 10 RxD P3.0 Pin Function P3 Bit
- 25. 3.2.3 畛nh th狸 CPU Chu k畛 l畛nh, chu k畛 m叩y v tr畉ng th叩i 25
- 26. 12MHz internal clock 6 state cycles 26
- 27. D畛n k棚nh bus 畛a ch畛 (byte th畉p) v bus d畛 li畛u 27
- 28. Truy c畉p b畛 nh畛 ch動董ng tr狸nh b棚n ngoi 28
- 29. 29
- 30. 30
- 31. 31
- 32. 3.2.4 C畉u tr炭c b畛 nh畛 8051 32
- 33. T坦m t畉t b畛 nh畛 d畛 li畛u tr棚n chip 33
- 34. B畛 nh畛 d畛 li畛u 8051 34
- 35. Lower 128 Bytes of Internal RAM 35 20H-2FH: 128 Bit-addressable bits occupying bit address 00H-7FH. 30H-7FH: General purpose RAM (can be accessed through direct or indirect addressing)
- 36. Upper 128 Bytes of Internal RAM 36
- 37. V湛ng nh畛 8032/8052 37 MOV A, 5FH MOV A, FFH MOV Ri, #5FH ( I = 0 or 1) MOV A, @Ri
- 38. T坦m t畉t thanh ghi PSW 38
- 39. T坦m t畉t thanh ghi PCON 39
- 40. Truy c畉p b畛 nh畛 ch動董ng tr狸nh b棚n ngoi 40
- 41. 畛nh th狸 畛c b畛 nh畛 ch動董ng tr狸nh b棚n ngoi (PCH byte c畛a PC v PCL l byte th畉p c畛a PC) 41 /PSEN 畛 m畛c th畉p trong th畛i gian l畉y l畛nh
- 42. Truy c畉p b畛 nh畛 d畛 li畛u b棚n ngoi 42
- 43. Gi畉n 畛 畛nh th狸 cho l畛nh MOVX 43
- 44. M畉ch gi畉i m達 畛a ch畛 c叩c EPROM 8KB v RAM 8KB v畛i h畛 8051 44
- 45. Ph畛 l畉p v湛ng nh畛 d畛 li畛u v ch動董ng tr狸nh b棚n ngoi 45
- 46. 3.2.8 Ho畉t 畛ng reset 46
- 47. M畉ch reset h畛 th畛ng 47 Vc(0+) = Vc(0-)
- 48. C叩c gi叩 tr畛 thanh ghi sau khi reset h畛 th畛ng 48