Led ASIC Power for the largest unit in GPU, participated in power study, power reduction, BA power estimation, and Di/Dt noise reduction.
Led GK208 ASIC & Bringup. Participated from Timing closure review, Tapeout review, ASIC bringup, to production.
Led unit RTL power reduction for GPU/Kepler series and two Tegra chips.
Led a FPGA project. A 15-Xilinx FPGA based system with 2300+ pairs LVDS running at 500+MHz. Supported PCIe/DP/HDMI/VGA/etc.
Led GT218 GPU area reduction. Re-designed/optimized many 3D/GFX units
Led MPEG4/Divx, MSPPP, PMU HW units. Designed VC1/TF/etc.
Designed a non-blocking pipeline based 8-way associative L2 Cache controller including Out-Of-Order data support.
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