* EDA tool development upon large code base using c/c++/perl
* Good knowledge of chip design flow from RTL to GDSII ( work experience in Logic Synthesis, IO DRC, Floorplan Auto-partition, Power Integrity Analysis flows, GDSII checks)
* Good knowledge of Industry standard file formats (VHDL,Verilog,LEF,DEF,OpenAccess) and Data strucutres.
Specialties: c++/java,software product development
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