- Experience in RTL Design (VHDL/Verilog), Verification and Validation
- Experience in developing FPGA verification plan, test plan, test cases and test bench for various system environment. Knowledge on C based verification
- Hands-on experience in high speed SERDES data path and DDR memory interface
- Good understanding on control plane buses like I2C, SPI, UART
- Hands-on experience in Linting, CDC and multi-clock design
- Hands-on experience on 3G UMTS layer-1 CRP algorithms and design partitioning across multiple FPGAs
- Knowledge on LTE PHY layer 3GPP Release 8 standards and CPRI protocols
- Knowledge on LTE channel estimation algorithms
- Performance analysis of DOA Estimation (M...
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