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Singapore Singapore
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Project Executive at Singapore University of Technology and Design
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Co-author papers:
(1) EDL, Vol. 32, No. 6, pp.716-718, (2011).
(2) Physical analysis of breakdown in high-¦Ê / metal gate stacks using TEM/EELS and STM for reliability enhancement, Invited Paper, INFOS, France, 2011.
(3) Evidence for compliance controlled oxygen vacancy and metal filament based resistive switching mechanisms in RRAM, INFOS, France, 2011.
(4) Random telegraph noise reduction in metal gate high-¦Ê stacks by bipolar switching and the performance boosting technique, IRPS, USA, 2011.
(5) EDL, Vol. 32, No. 4, pp.455-457, (2011).
(6) EDL, Vol. 32, No. 3, pp.252-254, (2011).
(7) An overview of physical analysis of nanosize conductive path in ultra-thin SiON and high-¦Ê gate die...
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