VLSI Domain Skills
HDLs: Verilog
HVL: System Verilog
TB Methodology: UVM
Scripting Language: TCL - TK
EDA Tool: Xilinx ISE, Modelsim, QuestaSim
Protocols: AMBA-ASB,NOC
Domain: ASIC/FPGA Design Flow,
Digital Design & Verification methodologies
Knowledge: RTL Coding, FSM based design, Simulation,
Good understanding of the ASIC and FPGA design flow
Experience in writing RTL models in Verilog HDL and
Testbenches in SystemVerilog
Very good understanding in verification methodologies UVm
Good knowledge of TCL-TK, Shell Scripting
Very good knowledge of Windows & UNIX Operating System
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