Personal Information
Organization / Workplace
Rio de Janeiro, Brazil Brazil
Occupation
Electronic Engineer
Industry
Government / Military
About
I am EE, M.Sc. with 20+ years experience
in designing and verifying SoC and FPGA devices
including Xilinx, Altera.
RTL Languages I use are VHDL and Verilog.
I perform Lab debug using Logic Analyzers and Oscilloscopes.
Contact Details