Personal Information
Organization / Workplace
Yongin, Gyeonggi-do, Korea Korea, South
Occupation
asic engineer at SK hynix
About
Good Skill :
- RTL design about ISP of CIS device
- DFTC, Design Compiler
- Power-Compiler(UPF,Low power)
- PrimeTime/PT-SI
- Formality, TetraMAX(ATPG,FA)
- Spyglass-DFT/Constraints
- RTL design for SCAN, BIST, Digital
- Image Signal Processing IP for CIS
- Visible enhancement IP
- Video Processing IP
Contact Details