Physical Design : Netlist to GDSII Flow
- Worked on 16nm technology in Cadence Encounter
- worked on 90nm technology Block implementation in IC compiler
- Worked on CLP for 14nm and 16nm
- (Netlist - Floor Planning - Placement - Clock-tree Synthesis - Routing -Signoff),
EDA TOOLS:
First Encounter, Prime Time, IC Validator, Encouter Conformal Low Power
We鈥檝e updated our privacy policy so that we are compliant with changing global privacy regulations and to provide you with insight into the limited ways in which we use your data.
You can read the details below. By accepting, you agree to the updated privacy policy.
