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Bengaluru Area, India India

Physical Design Engineer

Electronics / Computer Hardware

Physical Design : Netlist to GDSII Flow - Worked on 16nm technology in Cadence Encounter - worked on 90nm technology Block implementation in IC compiler - Worked on CLP for 14nm and 16nm - (Netlist - Floor Planning - Placement - Clock-tree Synthesis - Routing -Signoff), EDA TOOLS: First Encounter, Prime Time, IC Validator, Encouter Conformal Low Power