ºÝºÝߣ

ºÝºÝߣShare a Scribd company logo
manisudabathula

mani sudabathula

Personal Information
Organization / Workplace
India India
Occupation
--Seeking Entry Level FPGA Design/ ASIC Verification Engineer Position
About
Summary of Qualifications Good understanding of the ASIC and FPGA design flow Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog Very good knowledge in verification methodologies Good knowledge of Digitial Design Concepts Experience in using industry standard EDA tools for the front-end design and verification
Contact Details