--Seeking Entry Level FPGA Design/ ASIC Verification Engineer Position
About
Summary of Qualifications
Good understanding of the ASIC and FPGA design flow
Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog
Very good knowledge in verification methodologies
Good knowledge of Digitial Design Concepts
Experience in using industry standard EDA tools for the front-end design and verification
We鈥檝e updated our privacy policy so that we are compliant with changing global privacy regulations and to provide you with insight into the limited ways in which we use your data.
You can read the details below. By accepting, you agree to the updated privacy policy.
