Skilled, creative ASIC Physical design engineer with 7 years experience in ASIC design flow.
Have the experience of working in different technology node ranging from 90nm to 28nm.
Working as top level implementation engineer of multimillion gate designs which are area, time and power constrained. Main focus .
Expertise in Flood plan, constraint clean, CTS, timing sign-off and lower power methods, physical
level verification, power integrity.
Mentoring and leading junior members.
Enhancement of the PD flows in collaboration with EDA team.
Has experience of Working with foundry teams and IP providers in developing IPs for new process nodes.
Skill set: Physical Design ( Cadenc...
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