狠狠撸

Bengaluru Area, India India

FPGA& RTL DESIGN ENGINEER at MINDFLOW

Electronics / Computer Hardware

飪� Overall experience of 2.8 years in RTL Design & FPGA board design 飪� Experience in RTL design, Microarchitecture, On-chip debugging. 飪� Experience in writing Verilog testbench for simulating RTL design before implementing on FPGAs 飪� Good working knowledge on Xilinx FPGA and development tools 鈥�Good Experience SOC and ARM Architecture 鈥�Excellent understanding of Protocols such as AMBA AXI4 . 鈥� good knowledge of Modelsim, Questasim tools. Familiar with Object Oriented Programming. Area of Interest: Digital System Design, VLSI Design, Embedded System Design. IP design & verification SKILL SET *** HDL鈥檚 : Verilog ===== ===== ================== EDA Tools : QuestaSim (Mentor...