Objective
To utilize, develop my technical expertise and align with company goals and work with global clients.
Proficient:
鈥� Experience in writing RTL models in Verilog HDL and Testbenches in System Verilog.
鈥� Good understanding of the ASIC design flow and Digital Design.
鈥� Expertise in RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage,
Synthesis.
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