Having 1yr experience in Semiconductor Industry involved in the activities ranging from RTL to GDSII
* Digital Design, Verilog HDL
* Involved in Physical Design activities anything ranging from RTL to GDSII
* Comprehensive understanding of methodologies of Floor Planning, Power Planning, PnR, Extraction, IR Drop Analysis, STA Signoff, Layout, Physical Verification (DRC, LVS, ERC, Functional Verification) and deep sub-micron issues
* Expertise in Layout and Physical Verification
* Expertise in STA sign-off
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